Design methodology for fine-grained leakage control in MTCMOS
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2003 international symposium on Low power electronics and design
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Device optimization for ultra-low power digital sub-threshold operation
Proceedings of the 2004 international symposium on Low power electronics and design
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power-Delay Metrics Revisited for 90nm CMOS Technology
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
User-perceived latency driven voltage scaling for interactive applications
Proceedings of the 42nd annual Design Automation Conference
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
Proceedings of the 2006 international symposium on Low power electronics and design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy optimization of multiprocessor systems on chip by voltage selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Leakage current optimization techniques during test based on don't care bits assignment
Journal of Computer Science and Technology
Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits
Microelectronics Journal
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
VLSI interconnect repeater for sub-threshold applications: a novel approach
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
Efficient interconnect design with novel repeater insertion for low power applications
WSEAS Transactions on Circuits and Systems
Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Quasi-static voltage scaling for energy minimization with time constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Off-path leakage power aware routing for SRAM-based FPGAs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Statistical thermal modeling and optimization considering leakage power variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We present a Dynamic VTH Scaling (DVTS) scheme tosave the leakage power during active mode of the circuit.The power saving strategy of DVTS is similar to that of theDynamic VDD Scaling (DVS) scheme, which adaptivelychanges the supply voltage depending on the currentworkload of the system. Instead of adjusting the supplyvoltage, DVTS controls the threshold voltage by means ofbody bias control, in order to reduce the leakage power.The power saving potential of DVTS and its impact ondynamic and leakage power when applied to futuretechnologies are discussed. Pros and cons of the DVTSsystem are dealt with in detail. Finally, a feedback loophardware for the DVTS which tracks the optimal VTH for agiven clock frequency, is proposed. Simulation results showthat 92% energy savings can be achieved with DVTS for70nm circuits.