Leakage Power Analysis and Reduction for Nanoscale Circuits

Authors:
Amit Agarwal;Saibal Mukhopadhyay;Arijit Raychowdhury;Kaushik Roy;Chris H. Kim
Affiliations:
Intel Corp.;Purdue University;Purdue University;Purdue University;University of Minnesota
Venue:
IEEE Micro
Year:
2006

Citing 13
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Abstract

Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.