Fundamentals of modern VLSI devices

Optimization of VDD and VTH for low-power and high speed applications

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

VTCMOS characteristics and its optimum conditions predicted by a compact analytical model

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design

Enchanced multi-threshold (MTCMOS) circuits using variable well bias

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design

Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design

Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design

Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (alpha-power law model)

Proceedings of the 2002 international symposium on Low power electronics and design

Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS

Proceedings of the 2002 international symposium on Low power electronics and design

Subthreshold leakage modeling and reduction techniques

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling

Proceedings of the 40th annual Design Automation Conference

A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

A forward body-biased low-leakage SRAM cache: device and architecture considerations

Proceedings of the 2003 international symposium on Low power electronics and design

A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime

Proceedings of the 2003 international symposium on Low power electronics and design

Optimal body bias selection for leakage improvement and process compensation over different technology generations

Proceedings of the 2003 international symposium on Low power electronics and design

Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation

Proceedings of the 2003 international symposium on Low power electronics and design

Strained-si devices and circuits for low-power applications

Proceedings of the 2003 international symposium on Low power electronics and design

Influence of channel width on n- and p-type nano-wire-MOSFETs on silicon on insulator substrate

Microelectronic Engineering

Gate leakage reduction for scaled devices using transistor stacking

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Leakage in nano-scale technologies: mechanisms, impact and design considerations

Proceedings of the 41st annual Design Automation Conference

Toward a methodology for manufacturability-driven design rule exploration

Proceedings of the 41st annual Design Automation Conference

Novel sizing algorithm for yield improvement under process variation in nanometer technology

Proceedings of the 41st annual Design Automation Conference

Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era

Proceedings of the 41st annual Design Automation Conference

Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS

Proceedings of the 2004 international symposium on Low power electronics and design

Device optimization for ultra-low power digital sub-threshold operation

Proceedings of the 2004 international symposium on Low power electronics and design

A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations

Proceedings of the 2004 international symposium on Low power electronics and design

Low-power circuits and technology for wireless digital systems

IBM Journal of Research and Development

A New Crosstalk Noise Model for DOMINO Logic Circuits

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Pulsed wave interconnect

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Reverse-body bias and supply collapse for low effective standby power

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Leakage current estimation of CMOS circuit with stack effect

Journal of Computer Science and Technology - Special issue on computer graphics and computer-aided design

Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Statistical Timing Analysis using Levelized Covariance Propagation

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Analytical Study of Impact Ionization and Subthreshold Current in Submicron n-MOSFET

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Simulating and Improving Microelectronic Device Reliability by Scaling Voltage and Temperature

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Logic-based eDRAM: origins and rationale for use

IBM Journal of Research and Development - Electrochemical technology in microelectronics

Challenges and design choices in nanoscale CMOS

ACM Journal on Emerging Technologies in Computing Systems (JETC)

Explaining the gap between ASIC and custom power: a custom perspective

Proceedings of the 42nd annual Design Automation Conference

A novel synthesis approach for active leakage power reduction using dynamic supply gating

Proceedings of the 42nd annual Design Automation Conference

Full-chip analysis of leakage power under process variations, including spatial correlations

Proceedings of the 42nd annual Design Automation Conference

Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design

Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design

A Feasibility Study of Subthreshold SRAM Across Technology Generations

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Thermal Management of On-Chip Caches Through Power Density Minimization

Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture

Characterisation of a new hump-free device structure for smart power and embedded memory technologies

Microelectronic Engineering

Statistical design and optimization of SRAM cell for yield enhancement

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Robust analytical gate delay modeling for low voltage circuits

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Area optimization for leakage reduction and thermal stability in nanometer scale technologies

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Double edge triggered Feedback Flip-Flop in sub 100NM technology

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Vector extraction for average total power estimation

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Impact of NBTI on SRAM Read Stability and Design for Reliability

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI

Double-gate SOI devices for low-power and high-performance applications

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Leakage Power Analysis and Reduction for Nanoscale Circuits

IEEE Micro

Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits

Journal of Electronic Testing: Theory and Applications

Nanometer scale technologies: device considerations

Nano, quantum and molecular computing

Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques

Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events

Proceedings of the 43rd annual Design Automation Conference

Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM

Proceedings of the 43rd annual Design Automation Conference

A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates

Proceedings of the 43rd annual Design Automation Conference

Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Efficient testing of SRAM with optimized March sequences and a novel DFT technique for emerging failures due to process variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Analysis of super cut-off transistors for ultralow power digital logic circuits

Proceedings of the 2006 international symposium on Low power electronics and design

Robust level converter design for sub-threshold logic

Proceedings of the 2006 international symposium on Low power electronics and design

A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting

Proceedings of the 2006 international symposium on Low power electronics and design

Variability-aware device optimization under ION and leakage current constraints

Proceedings of the 2006 international symposium on Low power electronics and design

Continuous MOSFET performance increase with device scaling: the role of strain and channel material innovations

IBM Journal of Research and Development - Advanced silicon technology

Product-representative "At speed" test structures for CMOS characterization

IBM Journal of Research and Development - Advanced silicon technology

Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Prediction of leakage power under process uncertainties

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Non-classical hot-electron mechanism and its implications on the reliability and scalability of the high- κ dielectric N-MOS Flash memory cell

Microelectronic Engineering

Data remanence in semiconductor devices

SSYM'01 Proceedings of the 10th conference on USENIX Security Symposium - Volume 10

Interactive presentation: Process tolerant β-ratio modulation for ultra-dynamic voltage scaling

Proceedings of the conference on Design, automation and test in Europe

Data remanence in semiconductor devices

SSYM'01 Proceedings of the 10th conference on USENIX Security Symposium - Volume 10

Width-dependent statistical leakage modeling for random dopant induced threshold voltage shift

Proceedings of the 44th annual Design Automation Conference

Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications

Proceedings of the 44th annual Design Automation Conference

Characterization and estimation of circuit reliability degradation under NBTI using on-line IDDQ measurement

Proceedings of the 44th annual Design Automation Conference

Nanometer device scaling in subthreshold circuits

Proceedings of the 44th annual Design Automation Conference

Variation resilient low-power circuit design methodology using on-chip phase locked loop

Proceedings of the 44th annual Design Automation Conference

Thermal-aware methodology for repeater insertion in low-power VLSI circuits

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design

Power optimal MTCMOS repeater insertion for global buses

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design

Timing-driven row-based power gating

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design

Thermal-aware task scheduling at the system software level

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design

Minimizing the dynamic and sub-threshold leakage power consumption using least leakage vector-assisted technology mapping

Integration, the VLSI Journal

Dependence of electrical properties on interfacial layer of Ta2O5 films

Microelectronic Engineering

Thermal management of on-chip caches through power density minimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Parametric yield analysis and optimization in leakage dominated technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

The effect of process variation on device temperature in FinFET circuits

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Numerical simulation of random dopant fluctuation in sub-65 nm metal-oxide-semiconductor field effect transistors

MATH'05 Proceedings of the 8th WSEAS International Conference on Applied Mathematics

Full-chip leakage current estimation based on statistical sampling techniques

Proceedings of the 18th ACM Great Lakes symposium on VLSI

Comparison of the scaling characteristics of nanoscale SOI N-channel multiple-gate MOSFETs

Analog Integrated Circuits and Signal Processing

Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture

A methodology for statistical estimation of read access yield in SRAMs

Proceedings of the 45th annual Design Automation Conference

Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification

Proceedings of the 45th annual Design Automation Conference

A probabilistic technique for full-chip leakage estimation

Proceedings of the 13th international symposium on Low power electronics and design

Power and performance tradeoffs with process variation resilient adaptive cache architectures

Proceedings of the 21st annual symposium on Integrated circuits and system design

Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation

Microelectronics Journal

A novel current reference based on subthreshold MOSFETs with high PSRR

Microelectronics Journal

Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO

Microelectronics Journal

Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Thermal-aware methodology for repeater insertion in low-power VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Estimation for Speed and Leakage Power of Dual Threshold Domino OR Based on Wavelet Neural Networks

ISNN '09 Proceedings of the 6th International Symposium on Neural Networks on Advances in Neural Networks

Optimization and process variation analysis of nano-scale transistors

ICC'08 Proceedings of the 12th WSEAS international conference on Circuits

Device and circuit design challenges in the digital subthreshold region for ultralow-power applications

VLSI Design

A low-leakage open-loop frequency synthesizer allowing small-area on-chip loop filter

IEEE Transactions on Circuits and Systems II: Express Briefs

Suppression of corner effects in wide-channel triple-gate bulk FinFETs

Microelectronic Engineering

Scaling the gate dielectric: materials, integration, and reliability

IBM Journal of Research and Development

Picosecond imaging circuit analysis

IBM Journal of Research and Development

Organic thin-film transistors: a review of recent advances

IBM Journal of Research and Development

SOI technology for the GHz era

IBM Journal of Research and Development

Why BiCMOS and SOI BiCMOS?

IBM Journal of Research and Development

Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

IBM Journal of Research and Development

CMOS design near the limit of scaling

IBM Journal of Research and Development

Improving cache lifetime reliability at ultra-low voltages

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture

Probabilistic analysis and design of metallic-carbon-nanotube-tolerant digital logic circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Adaptive sampling for efficient failure probability analysis of SRAM cells

Proceedings of the 2009 International Conference on Computer-Aided Design

Yield estimation of SRAM circuits using "Virtual SRAM Fab"

Proceedings of the 2009 International Conference on Computer-Aided Design

Switching and leakage power modeling for multiple-supply dynamic gate with delay constraining based on wavelet neural networks

IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks

Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques

A 0.6-V delta-sigma modulator with subthreshold-leakage suppression switches

IEEE Transactions on Circuits and Systems II: Express Briefs

Energy-efficient embedded system design at 90nm and below: a system-level perspective

ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems

Variation-aware software techniques for cache leakage reduction using value-dependence of SRAM leakage due to within-die process variation

HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers

Statistical design of the 6T SRAM bit cell

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Methodology of statistical RTS noise analysis with charge-carrier trapping models

IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009

Leakage-delay tradeoff in FinFET logic circuits: a comparative analysis with bulk technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

On-chip variability sensor using phase-locked loop for detecting and correcting parametric timing failures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DFT and minimum leakage pattern generation for static power reduction during test and burn-in

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS

Proceedings of the 47th Design Automation Conference

A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

Full-chip leakage analysis for 65nm CMOS technology and beyond

Integration, the VLSI Journal

A design-oriented soft error rate variation model accounting for both die-to-die and within-die variations in submicrometer CMOS SRAM cells

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Characterization of random process variations using ultralow-power, high-sensitivity, bias-free sub-threshold process sensor

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Ground-bouncing-noise-aware combinational MTCMOS circuits

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits

Proceedings of the Conference on Design, Automation and Test in Europe

TRAM: a tool for temperature and reliability aware memory design

Proceedings of the Conference on Design, Automation and Test in Europe

Low-power multimedia system design by aggressive voltage scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

High speed interconnect through device optimization for subthreshold FPGA

Microelectronics Journal

A scalable circuit-architecture co-design to improve memory yield for high-performance processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A novel variation-tolerant keeper architecture for high-performance low-power wide fan-in dynamic OR gates

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Low power and high speed multi threshold voltage interface circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Oxide roughness induced fluctuation effects in nanoscale MOSFET devices

MINO'06 Proceedings of the 5th WSEAS international conference on Microelectronics, nanoelectronics, optoelectronics

Random doping induced fluctuations in p-n junction diodes

ICECS'05 Proceedings of the 4th WSEAS international conference on Electronics, control and signal processing

Software-level instruction-cache leakage reduction using value-dependence of SRAM leakage in nanometer technologies

Transactions on high-performance embedded architectures and compilers III

Analytical soft error models accounting for die-to-die and within-die variations in sub-threshold SRAM cells

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Body bias voltage computations for process and temperature compensation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A design-specific and thermally-aware methodology for trading-off power and performance in leakage-dominant CMOS technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

Journal of Computational Electronics

Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations

CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Advancement in nanoscale CMOS device design en route to ultra-low-power applications

VLSI Design

Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design

Proceedings of the International Conference on Computer-Aided Design

A clock generator driven by a Unified-CBiCMOS buffer driver for high speed and low energy operation

PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications

ACM Transactions on Embedded Computing Systems (TECS)

Stepwise sleep depth control for run-time leakage power saving

Proceedings of the great lakes symposium on VLSI

Impact of dual-k spacer on analog performance of underlap FinFET

Microelectronics Journal

Quantum mechanical effects on the threshold voltage of surrounding-gate MOSFETs

Microelectronics Journal

The potential of Fe-FET for robust design under variations: A compact modeling study

Microelectronics Journal

First integration of MOSFET band-to-band-tunneling current in BSIM4

Microelectronics Journal

A 0.6-V subthreshold-leakage suppressed fully differential CMOS switched-capacitor amplifier

Analog Integrated Circuits and Signal Processing

An analytical model of threshold voltage for short-channel double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs

Journal of Computational Electronics

CLIP: circuit level IC protection through direct injection of process variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Independently-controlled-gate FinFET schmitt trigger sub-threshold SRAMs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Testing methodology of embedded DRAMs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Statistical SRAM read access yield improvement using negative capacitance circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Constant delay logic style

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Impact of elliptical cross-section on the propagation delay of multi-channel gate-all-around MOSFET based inverters

Microelectronics Journal

Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells

Microelectronics Journal