Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Sleep switch dual threshold voltage domino logic with reduced standby leakage current
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
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An approach for estimating the leakage power and the speed of the dual threshold domino OR gates based on Wavelet Neural Networks (WNN) in 45 nm technology is proposed. The estimating system has fast convergence and high precision. By studying the impact of the dual threshold voltage technique (DTV) on leakage reduction and delay increase, it successfully estimates the nonlinear changing of the leakage power and delay of the different inputs domino OR gates. At last, the reason for the estimating error and the trend of the estimating curve are explained, respectively.