ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sleep switch dual threshold voltage domino logic with reduced standby leakage current
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Process variation aware cache leakage management
Proceedings of the 2006 international symposium on Low power electronics and design
Domino logic with variable threshold voltage keeper
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Estimation for Speed and Leakage Power of Dual Threshold Domino OR Based on Wavelet Neural Networks
ISNN '09 Proceedings of the 6th International Symposium on Neural Networks on Advances in Neural Networks
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
Low power and high performance dynamic CMOS XOR/XNOR gate design
Microelectronic Engineering
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The inputs and clock signals combination sleep state dependent leakage current characteristics is analyzed and the optimal sleep state is examined in sub-65nm dual V"t footed domino circuits. Simulations based on 65 and 45nm BSIM4 models show that the conventional CHIL state (the clock signal is high and inputs are all low) is ineffective for lowering the leakage current and the conventional CHIH state (the clock signal and inputs are all high) is only effective to suppress the leakage current at high temperature other than the high fan-in domino circuits. For the high fan-in footed domino circuits at high temperature and most of footed domino circuits at room temperature, the CLIL (the clock signal and inputs are all low) state is preferable to reduce the leakage current. Further, the influence of the process variations on the leakage current characteristics of the dual V"t footed domino circuits is also evaluated. It is observed that the average leakage current is universally higher than the date reported in the normal corner and the CLIL state is the optimum choice considering the leakage current reduction and the robustness to the process variations simultaneously.