Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Automated selective multi-threshold design for ultra-low standby applications
Proceedings of the 2002 international symposium on Low power electronics and design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ
ITC '00 Proceedings of the 2000 IEEE International Test Conference
The Future of Delta IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Design methodology for fine-grained leakage control in MTCMOS
Proceedings of the 2003 international symposium on Low power electronics and design
An MTCMOS design methodology and its application to mobile computing
Proceedings of the 2003 international symposium on Low power electronics and design
Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Characterization and modeling of run-time techniques for leakage power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents
Proceedings of the 42nd annual Design Automation Conference
Efficient and scalable compiler-directed energy optimization for realtime applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Leakage-delay tradeoff in FinFET logic circuits: a comparative analysis with bulk technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Post-manufacture tuning for nano-CMOS yield recovery using reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic synthesis of near-threshold circuits with fine-grained performance tunability
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Domino logic with variable threshold voltage keeper
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance CMOS circuit by using charge recycling active body-bias controlled SOI
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
Integration, the VLSI Journal
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