Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ

Authors:
Ali Keshavarzi;Kaushik Roy;Charles F. Hawkins;Vivek De
Affiliations:
Microprocessor Research Labs, Intel Corporation, Hillsboro, OR;Purdue University, West Lafayette, IN;The University of New Mexico, Albuquerque, NM;Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Year:
2003

Citing 15
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Abstract

Technology scaling challenges the effectiveness of current-based test techniques such as IDDQ. Furthermore, existing leakage reduction techniques are not as effective in aggressively scaled technologies. We exploited intrinsic dependencies of transistor and circuit leakage on clock frequency, temperature, and reverse body bias (RBB) to discriminate fast ICs from defective ones. Transistor and circuit parameters were measured and correlated to demonstrate leakage-based testing solutions with improved sensitivity. We used a test IC with available body terminals for our experimental measurements. Our data suggest adopting a sensitive multiple-parameter test solution. For high performance IC applications, we propose a new test technique, IDDQ versus FMAX (maximum operating frequency), in conjunction with using temperature (or RBB) to improve the defect detection sensitivity. For cost sensitive applications, IDDQ versus temperature test can be deployed. Our data show that temperature (cooling from 110 °C to room) improved sensitivity of IDDQ versus FMAX two-parameter test by more than an order of magnitude (13.8x). The sensitivity can also be tuned by proper selection of a temperature range to match a required defect per million (DPM) level.