Technology and design challenges for low power and high performance

A static power model for architects

Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

Physical layer driven protocol and algorithm design for energy-efficient wireless sensor networks

Proceedings of the 7th annual international conference on Mobile computing and networking

Scaling of stack effect and its application for leakage reduction

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design

Analysis of dual-Vt SRAM cells with full-swing single-ended bit line sensing for on-chip cache

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Dynamic fine-grain leakage reduction using leakage-biased bitlines

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture

Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS

Proceedings of the 2002 international symposium on Low power electronics and design

Low-leakage asymmetric-cell SRAM

Proceedings of the 2002 international symposium on Low power electronics and design

TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator

PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers

Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations

Proceedings of the 40th annual Design Automation Conference

Energy-efficient skewed static logic with dual Vt: design and synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)

Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ

ITC '00 Proceedings of the 2000 IEEE International Test Conference

High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation

Proceedings of the 2003 international symposium on Low power electronics and design

Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

Energy-efficient communication for high density networks

Ambient intelligence

Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era

Proceedings of the 41st annual Design Automation Conference

Wire Delay is Not a Problem for SMT (In the Near Future)

Proceedings of the 31st annual international symposium on Computer architecture

Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Power-optimal pipelining in deep submicron technology

Proceedings of the 2004 international symposium on Low power electronics and design

Noise-tolerant high fan-in dynamic CMOS circuit design

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

A high speed and leakage-tolerant domino logic for high fan-in gates

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

Challenges and design choices in nanoscale CMOS

ACM Journal on Emerging Technologies in Computing Systems (JETC)

A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Benefits and Costs of Power-Gating Technique

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Thermal Management of On-Chip Caches Through Power Density Minimization

Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture

Power reduction techniques for microprocessor systems

ACM Computing Surveys (CSUR)

Measuring the gap between FPGAs and ASICs

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Area optimization for leakage reduction and thermal stability in nanometer scale technologies

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Compilers for leakage power reduction

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Nanometer scale technologies: device considerations

Nano, quantum and molecular computing

Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events

Proceedings of the 43rd annual Design Automation Conference

Energy-efficient soft error-tolerant digital signal processing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance

Proceedings of the 2006 international symposium on Low power electronics and design

Floorplan driven leakage power aware IP-based SoC design space exploration

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

Minimizing peak power in synchronous logic circuits

Proceedings of the 17th ACM Great Lakes symposium on VLSI

An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

High performance low power CMOS dynamic logic for arithmetic circuits

Microelectronics Journal

Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications

Proceedings of the 44th annual Design Automation Conference

Thermal management of on-chip caches through power density minimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Parametric yield analysis and optimization in leakage dominated technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

On Composite Leakage Current Maximization

Journal of Electronic Testing: Theory and Applications

A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

ThermalScope: multi-scale thermal analysis for nanometer-scale integrated circuits

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Statistical modeling and analysis of chip-level leakage power by spectral stochastic method

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Design and application of adaptive delay sequential elements

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Multiscale thermal analysis for nanometer-scale integrated circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Statistical modeling and analysis of chip-level leakage power by spectral stochastic method

Integration, the VLSI Journal

An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects

Proceedings of the 2009 International Conference on Computer-Aided Design

A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation

Proceedings of the 47th Design Automation Conference

TRAM: a tool for temperature and reliability aware memory design

Proceedings of the Conference on Design, Automation and Test in Europe

Design constraint of fine grain supply voltage control LSI

Proceedings of the 16th Asia and South Pacific Design Automation Conference

Analysis and optimization of nanometer CMOS circuits for soft-error tolerance

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A leakage-tolerant low-swing circuit style in partially depleted silicon-on-insulator CMOS technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)

Test data compression using selective encoding of scan slices

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A design-specific and thermally-aware methodology for trading-off power and performance in leakage-dominant CMOS technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates

Integration, the VLSI Journal

Impact of NBTI on performance of domino logic circuits in nano-scale CMOS

Microelectronics Journal

Compiler analysis and supports for leakage power reduction on microprocessors

LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing

Fast Statistical Full-Chip Leakage Analysis for Nanometer VLSI Systems

ACM Transactions on Design Automation of Electronic Systems (TODAES)