IBM experiments in soft fails in computer electronics (1978–1994)
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Field testing for cosmic ray soft errors in semiconductor memories
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
Latch Design for Transient Pulse Tolerance
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Reliability Enhancement of Analog-to-Digital Converters (ADCs)
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A Study of the Error Behavior of a 32-bit RISC Subjected to Simulated Transient Fault Injection
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Some Issues in Gray Code Addressing
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Transient Fault Sensitivity Analysis of Analog-to-Digital Converters (ADCs)
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Effects and detection of intermittent failures in digital systems
AFIPS '69 (Fall) Proceedings of the November 18-20, 1969, fall joint computer conference
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Cache size selection for performance, energy and reliability of time-constrained systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exact Fault-Sensitive Feasibility Analysis of Real-Time Tasks
IEEE Transactions on Computers
SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Image enhancement for backlight-scaled TFT-LCD displays
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-overhead and reliable switch architecture for Network-on-Chips
Integration, the VLSI Journal
Soft error-aware design optimization of low power and time-constrained embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
An energy-aware active smart card
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware dependability in the presence of soft errors
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
ACM Transactions on Embedded Computing Systems (TECS)
Coupling induced soft error mechanisms in nanoscale CMOS technologies
Analog Integrated Circuits and Signal Processing
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High fault tolerance for transient faults and low-power consumption are key objectives in the design of critical embedded systems. Systems like smart cards, PDAs, wearable computers, pacemakers, defibrillators, and other electronic gadgets must not only be designed for fault tolerance but also for ultra-low-power consumption due to limited battery life. In this paper, a highly accurate method of estimating fault tolerance in terms of mean time to failure (MTTF) is presented. The estimation is based on circuit-level simulations (HSPICE) and uses a double exponential current-source fault model. Using counters, it is shown that the transient fault tolerance and power dissipation of low-power circuits are at odds and allow for a power fault-tolerance tradeoff. Architecture and circuit level fault tolerance and low-power techniques are used to demonstrate and quantify this tradeoff. Estimates show that incorporation of these techniques results either in a design with an MTTF of 36 years and power consumption of 102 µW or a design with an MTTF of 12 years and power consumption of 20 µW. Depending on the criticality of the system and the power budget, certain techniques might be preferred over others, resulting in either a more fault tolerant or a lower power design, at the sacrifice of the alternative objective.