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Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
Proceedings of the conference on Design, automation and test in Europe
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Microprocessors & Microsystems
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This paper proposes and evaluates Low-overhead, Reliable Switch (LRS) architecture to enhance the reliability of Network-on-Chips (NoCs). The proposed switch architecture exploits information and hardware redundancies to eliminate retransmission of faulty flits. The LRS architecture creates a redundant copy of each newly received flit and stores the redundant flit in a duplicated flit buffer that is associated with the incoming channel of the flit. Flit buffers in the LRS are equipped with information redundancy to detect probable bit flip errors. When an error is detected in a flit buffer, its duplicated buffer is used to recover the correct value of the flit. In this way, the propagation of the erroneous flits in NoC is prevented without any need to credit signals and, retransmission buffers. Using an HDL-based NoC simulator, the LRS is compared to two other widely used reliability enhancement methods: the Switch-to-Switch (S2S) and the End-to-End (E2E) methods. The simulation results show that the LRS consumes less power and provides higher performance compared to those of the E2E and S2S methods. More importantly, unlike the E2E and the S2S methods, the LRS has constant overheads, which makes it applicable in all working conditions. To validate the comparison, an analytical performance and reliability model is developed for the LRS, S2S and E2E methods. The results of the model match those obtained from the simulations while the proposed model is significantly faster.