Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz

Authors:
Yuanfang Hu;Hongyu Chen;Yi Zhu;Andrew A. Chien;Chung-Kuan Cheng
Affiliations:
Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA;Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA;Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA;Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA;Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA
Venue:
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Year:
2005

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Abstract

Power consumption has become one of the ?rst order design considerations of the nano-scale VLSI designs. In this paper, we propose a methodology to synthesize energy-ef?cient Networks-on-Chip (NoCs). Our methodology features three key characters. First, we adopt a multicommodity ?ow formulation to unify network topologies, physical embedding, and wire style optimizations. Second, we utilize a variety of interconnect wire styles to achieve high performance low power on-chip communication. Third, we heuristically explore a large design space of network topologies. Experiments on a homogeneous communication demand model demonstrate that for a 4脳4 NoC with torus topology, our methodology can achieve a power saving up to 35%.