Graph theory and its applications
Graph theory and its applications
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler Physical Compiler and Prime Time
Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler Physical Compiler and Prime Time
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IEEE Design & Test
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A low power approach to system level pipelined interconnect design
Proceedings of the 2004 international workshop on System level interconnect prediction
Topology optimization for application-specific networks-on-chip
Proceedings of the 2004 international workshop on System level interconnect prediction
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Managing power consumption in networks on chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Power-aware communication optimization for networks-on-chips with voltage scalable links
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors
IEEE Transactions on Computers
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Application-specific network-on-chip architecture customization via long-range link insertion
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Graph Theory: Modeling, Applications, and Algorithms
Graph Theory: Modeling, Applications, and Algorithms
An Analytical Performance Model for the Spidergon NoC
AINA '07 Proceedings of the 21st International Conference on Advanced Networking and Applications
A Power and Energy Exploration of Network-on-Chip Architectures
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Analytical router modeling for networks-on-chip performance analysis
Proceedings of the conference on Design, automation and test in Europe
Energy-aware synthesis of networks-on-chip implemented with voltage islands
Proceedings of the 44th annual Design Automation Conference
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Topological Structure and Analysis of Interconnection Networks
Topological Structure and Analysis of Interconnection Networks
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Power consumption of 3D networks-on-chips: Modeling and optimization
Microprocessors & Microsystems
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This paper analyzes the main sources of power consumption in Networks-on-Chip (NoC)-based systems. Analytical power models of global interconnection links are studied at different levels of abstraction. Additionally, power measurement experiments are performed for different types of routers. Based on this study, we propose a new topology-based methodology to optimize the power consumption of complex NoC-based systems at early design phases. The efficiency of the proposed methodology is verified through a case study of an MPEG4 video application. Experimental results show a promising improvement in power consumption (8.55%), average number of hops (10.80%), and number of global links (56.25%) compared to the best known related work.