The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Performance of data networks with random links
Mathematics and Computers in Simulation
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Networks on chip
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
An Interconnect Channel Design Methodology for High Performance Integrated Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Computation and communication refinement for multiprocessor SoC design: A system-level perspective
Proceedings of the 41st annual Design Automation Conference
Communication latency aware low power NoC synthesis
Proceedings of the 43rd annual Design Automation Conference
NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Designing efficient irregular networks for heterogeneous systems-on-chip
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Systems Architecture: the EUROMICRO Journal
ROAdNoC: runtime observability for an adaptive network on chip architecture
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Power optimization for application-specific networks-on-chips: A topology-based approach
Microprocessors & Microsystems
A DP-network for optimal dynamic routing in network-on-chip
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Automated technique for design of NoC with minimal communication latency
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Custom networks-on-chip architectures with multicast routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A methodology for constraint-driven synthesis of on-chip communications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Configurable links for runtime adaptive on-chip communication
Proceedings of the Conference on Design, Automation and Test in Europe
A holistic approach to network-on-chip synthesis
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design of network-on-chip architectures with a genetic algorithm-based technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-optimized on-chip networks using reconfigurable shortcut paths
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
A tree-based topology synthesis for on-chip network
Proceedings of the International Conference on Computer-Aided Design
A dynamically reconfigurable communication architecture for multicore embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
On bottleneck analysis in stochastic stream processing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Application-Specific Network-on-Chip synthesis with flexible router Placement
Journal of Systems Architecture: the EUROMICRO Journal
Analytical performance modeling of shuffle-exchange inspired mesh-based Network-on-Chips
Performance Evaluation
An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture
Wireless Personal Communications: An International Journal
Journal of Systems Architecture: the EUROMICRO Journal
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Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture where a few application-specific long-range links are inserted on top of a regular mesh network. This way, we can better exploit the benefits of both complete regularity and partial customization. Indeed, our experimental results show that inserting application-specific long-range links significantly increases the critical traffic workload at which the network state transits from a free to a congested regime. This, in turn, results in a significant reduction in the average packet latency and a major improvement in the network achievable throughput.