Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Express Cubes: Improving the Performance of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
A Framework for Designing Deadlock-Free Wormhole Routing Algorithms
IEEE Transactions on Parallel and Distributed Systems
A simple mathematical model of adaptive routing in wormhole k-ary n-cubes
Proceedings of the 2002 ACM symposium on Applied computing
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Design and Analysis of Even-Sized Binary Shuffle-Exchange Networks for Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Efficient deadlock-free wormhole routing in shuffle based networks
SPDP '95 Proceedings of the 7th IEEE Symposium on Parallel and Distributeed Processing
Performance Modeling of Fully Adaptive Wormhole Routing in 2-D Mesh-Connected Multiprocessors
MASCOTS '04 Proceedings of the The IEEE Computer Society's 12th Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Application-specific network-on-chip architecture customization via long-range link insertion
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
Flattened Butterfly Topology for On-Chip Networks
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
An accurate mathematical performance model of adaptive routing in the star graph
Future Generation Computer Systems
The Shuffle-Exchange Mesh Topology for 3D NoCs
ISPAN '08 Proceedings of the The International Symposium on Parallel Architectures, Algorithms, and Networks
Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Long-range dependence and on-chip processor traffic
Microprocessors & Microsystems
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
The 2D SEM: A novel high-performance and low-power mesh-based topology for networks-on-chip
International Journal of Parallel, Emergent and Distributed Systems - Performance evaluation of ubiquitous computing and networked systems
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Workload characterization and its impact on multicore platform design
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An analytical approach for network-on-chip performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical model for Network-on-Chip with finite input buffer
Frontiers of Computer Science in China
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI
Proceedings of the 49th Annual Design Automation Conference
Non-Stationary Traffic Analysis and Its Implications on Multicore Platform Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes and evaluates a shuffle-exchange as an efficient alternative to the popular mesh topology for Network-on-Chips (NoCs). Although the proposed topology imposes the cost equal to that of the mesh topology, the proposed topology (1) provides lower diameter for NoC, (2) offers better performance under uniform, hotspot, and matrix-transpose traffic patterns and (3) consumes lower energy for packet delivery. To speed up the evaluation process of the proposed topology, an analytical performance model is proposed in the paper to predict the performance of NoCs. The model uses a network of M/G/1 queues to consider channels of the NoC. In this way, the model accurately estimates the average message latency which is a widely used representative for the network performance. Results obtained from the analytical model are in good agreement with those of simulations for a wide range of working conditions (e.g. various network sizes, different message lengths, and different traffic patterns). The proposed analytical model provides a minimum of 400% speed-up in the evaluation process of the proposed topology.