A Unified theory of interconnection network structure
Theoretical Computer Science
Generalized de Bruijn digraphs
Networks
An Adaptation of the Fast Fourier Transform for Parallel Processing
Journal of the ACM (JACM)
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Memory-processor connection networks
Memory-processor connection networks
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
On shortest path routing in single stage shuffle-exchange networks
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
The Journal of Supercomputing
All-to-all personalized exchange in generalized shuffle-exchange networks
Theoretical Computer Science
A customized cross-bar for data-shuffling in domain-specific simd processors
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
Semi custom design: a case study on SIMD shufflers
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Analytical performance modeling of shuffle-exchange inspired mesh-based Network-on-Chips
Performance Evaluation
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The architecture and performance of binary shuffle-exchange networks of any size are investigated. It is established that a network with a shuffle-exchange stages whose number equals the least integer (or=log/sub 2/N) or a single recirculating stage can provide the connectivity between N inputs and N outputs using a distributed tag-based control algorithm. Control tags depend on both source and destination when N is not a power of two and can be computed in a simple manner. Several structural and dynamic properties of the network are established, contrasting the behavior of the power-of-two and composite sized systems. The performance of the network in a stochastic environment is investigated analytically. It is shown that the shuffle-exchange networks behave in much the same way with respect to traffic and buffer capacity regardless of whether the system size is a power of two or not.