Interconnection Networks: An Engineering Approach

Authors:
Jose Duato;Sudhakar Yalamanchili;Ni Lionel
Affiliations:
-;-;-
Venue:
Interconnection Networks: An Engineering Approach
Year:
2002

Citing 0
Cited 266

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10 A Four-Terabit Packet Switch Supporting Long Round-Trip Times

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Nonblocking k-Fold Multicast Networks

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Routing Permutations with Link-Disjoint and Node-Disjoint Paths in a Class of Self-Routable Interconnects

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FC3D: Flow Control-Based Distributed Deadlock Detection Mechanism for True Fully Adaptive Routing in Wormhole Networks

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Deadlock-Free Dynamic Reconfiguration Schemes for Increased Network Dependability

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Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach

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A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors

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Scalable Hardware-Based Multicast Trees

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A Memory-Effective Routing Strategy for Regular Interconnection Networks

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
HERMES: an infrastructure for low area overhead packet-switching networks on chip

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ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
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Routing Permutations on Baseline Networks with Node-Disjoint Paths

IEEE Transactions on Parallel and Distributed Systems
Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster

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Analytical Performance Comparison of Deterministic, Partially- and Fully-Adaptive Routing Algorithms in Binary n-Cubes

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IEEE Transactions on Parallel and Distributed Systems
On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect
Performance comparison of routing algorithms in wormhole-switched networks

Parallel Computing
Characterization of spatial fault patterns in interconnection networks

Parallel Computing
Profile-driven energy reduction in network-on-chips

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NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
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IEEE Transactions on Parallel and Distributed Systems
The performance of synchronous parallel polynomial root extraction on a ring multicomputer

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System level assessment of an optical NoC in an MPSoC platform

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An evolutionary approach to collective communication scheduling

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Performance analysis of fault-tolerant routing algorithm in wormhole-switched interconnections

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Enhanced fault tolerant routing algorithms using a concept of "balanced ring"

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Quasi-global routing for fault-tolerant high-performance interconnection networks

PDCN'07 Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: parallel and distributed computing and networks
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Communication delay analysis of fault-tolerant pipelined circuit switching in torus

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Analysis and optimization of prediction-based flow control in networks-on-chip

ACM Transactions on Design Automation of Electronic Systems (TODAES)
A New Cost-Effective Technique for QoS Support in Clusters

IEEE Transactions on Parallel and Distributed Systems
A Service-Centric Multicast Architecture and Routing Protocol

IEEE Transactions on Parallel and Distributed Systems
Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding

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Performance of deterministic and adaptive broadcast algorithms in multicomputer networks

International Journal of High Performance Computing and Networking
Multicast communication in OTIS-hypercube multi-computer systems

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Pipelined circuit switching: Analysis for the torus with non-uniform traffic

Journal of Systems Architecture: the EUROMICRO Journal
Performance modelling of pipelined circuit switching in hypercubes with hot spot traffic

Microprocessors & Microsystems
RTOIN: a new scalable optical interconnection network

Proceedings of the 2nd international conference on Scalable information systems
Designing efficient irregular networks for heterogeneous systems-on-chip

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Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions

Journal of Systems Architecture: the EUROMICRO Journal
Energy reduction through crosstalk avoidance coding in networks on chip

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Design issues in next-generation merchant switch fabrics

IEEE/ACM Transactions on Networking (TON)
QoS-supported on-chip communication for multi-processors

International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
3-D topologies for networks-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An evolutionary design technique for collective communications on optimal diameter-degree networks

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A proposal for managing ASI fabrics

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A Lightweight Fault-Tolerant Mechanism for Network-on-Chip

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A new general method to compute virtual channels occupancy probabilities in wormhole networks

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Dcell: a scalable and fault-tolerant network structure for data centers

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Multicast parallel pipeline router architecture for network-on-chip

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Some topological and combinatorial properties of WK-recursive mesh and WK-pyramid interconnection networks

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Performance Evaluation of Fully Adaptive Routing for the Torus Interconnect Networks

ICCS '07 Proceedings of the 7th international conference on Computational Science, Part IV: ICCS 2007
A Simple and Efficient Fault-Tolerant Adaptive Routing Algorithm for Meshes

ICA3PP '08 Proceedings of the 8th international conference on Algorithms and Architectures for Parallel Processing
An Adaptive and Fault-Tolerant Routing Algorithm for Meshes

ICCSA '08 Proceeding sof the international conference on Computational Science and Its Applications, Part I
On the Probability of Facing Fault Patterns: A Performance and Comparison Measure of Network Fault-Tolerance

ICCS '08 Proceedings of the 8th international conference on Computational Science, Part I
Reducing Packet Dropping in a Bufferless NoC

Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
Evolutionary Design of Fault Tolerant Collective Communications

ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
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On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers

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CTC: An end-to-end flow control protocol for multi-core systems-on-chip

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RecTOR: A New and Efficient Method for Dynamic Network Reconfiguration

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SpringSim '09 Proceedings of the 2009 Spring Simulation Multiconference
A networks-on-chip architecture design space exploration - The LIB

Computers and Electrical Engineering
FACT: fast communication trace collection for parallel applications through program slicing

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Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

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A new performance measure for characterizing fault rings in interconnection networks

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Locality-preserving randomized multicast routing on k-ary n-cube

ICOIN'09 Proceedings of the 23rd international conference on Information Networking
Routing direction determination in regular networks based on configurable circuits

Future Generation Computer Systems
Adaptive routing for convergence enhanced ethernet

HPSR'09 Proceedings of the 15th international conference on High Performance Switching and Routing
Analytical modelling of networks in multicomputer systems under bursty and batch arrival traffic

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ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
THIN: a new hierarchical interconnection network-on-chip for SOC

ICA3PP'07 Proceedings of the 7th international conference on Algorithms and architectures for parallel processing
A routing algorithm for random error tolerance in network-on-chip

HCI'07 Proceedings of the 12th international conference on Human-computer interaction: applications and services
Routing-contained virtualization based on Up*/Down* forwarding

HiPC'07 Proceedings of the 14th international conference on High performance computing
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Cross-line: a globally adaptive control method of interconnection network

ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
rHALB: a new load-balanced routing algorithm for k-ary n-cube networks

APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
A clustering model for multicast on hypercube network

GPC'08 Proceedings of the 3rd international conference on Advances in grid and pervasive computing
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ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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Performance analysis of communication networks in multi-cluster systems under bursty traffic with communication locality

GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Performance modelling and analysis of interconnection networks with spatio-temporal bursty traffic

GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Communication modeling of multicast in all-port wormhole-routed NoCs

Journal of Systems and Software
A Low-Latency and Memory-Efficient On-chip Network

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A Low-Cost Deadlock-Free Design of Minimal-Table Rerouted XY-Routing for Irregular Wireless NoCs

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Evolutionary-based conflict-free scheduling of collective communications on spidergon NoCs

Proceedings of the 12th annual conference on Genetic and evolutionary computation
Complement routing: A methodology to design reliable routing algorithm for Network on Chips

Microprocessors & Microsystems
Communication performance evaluation and analysis of a mesh system area network for high performance computers

MAMECTIS'10 Proceedings of the 12th WSEAS international conference on Mathematical methods, computational techniques and intelligent systems
Symbiotic routing in future data centers

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Performance modeling of n-dimensional mesh networks

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aEqualized: a novel routing algorithm for the Spidergon network on chip

Proceedings of the Conference on Design, Automation and Test in Europe
Exploring programming model-driven QoS support for NoC-based platforms

CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ERA: an efficient routing algorithm for power, throughput and latency in network-on-chips

NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
An efficient strategy for reducing head-of-line blocking in fat-trees

Euro-Par'10 Proceedings of the 16th international Euro-Par conference on Parallel processing: Part II
An analytical model of broadcast in QoS-aware wormhole-routed NoCs

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Performance modeling of Cartesian product networks

Journal of Parallel and Distributed Computing
Dynamic power saving in fat-tree interconnection networks using on/off links

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
On the probability distribution of busy virtual channels

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Software-based fault-tolerant routing algorithm in multi- dimensional networks

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Analytical performance modelling of partially adaptive routing in wormhole hypercubes

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A compiler-based communication analysis approach for multiprocessor systems

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Modeling and evaluation of ring-based interconnects for Network-on-Chip

Journal of Systems Architecture: the EUROMICRO Journal
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs

Journal of Systems Architecture: the EUROMICRO Journal
Customized computer-aided application mapping on NoC infrastructure using multi-objective optimization

Journal of Systems Architecture: the EUROMICRO Journal
A generic adaptive path-based routing method for MPSoCs

Journal of Systems Architecture: the EUROMICRO Journal
A networks-on-chip emulation/verification framework

International Journal of High Performance Systems Architecture
A unified design space simulation environment for network-on-chip: fuse-N

International Journal of High Performance Systems Architecture
A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip

Microprocessors & Microsystems
On an efficient NoC multicasting scheme in support of multiple applications running on irregular sub-networks

Microprocessors & Microsystems
Control for power gating of wires

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-aware multi-objective evolutionary optimization for application mapping on NoC platforms

IEA/AIE'10 Proceedings of the 23rd international conference on Industrial engineering and other applications of applied intelligent systems - Volume Part II
Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip

Microprocessors & Microsystems
Designing a Fault-tolerant Fully-Chained Combining Switches Multi-stage Interconnection Network with Disjoint Paths

The Journal of Supercomputing
"It's a small world after all": noc performance optimization via long-range link insertion

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms

Journal of Parallel and Distributed Computing
Performance study of multilayered multistage interconnection networks under hotspot traffic conditions

Journal of Computer Systems, Networks, and Communications
Performance evaluation of TOFU system area network design for high-performance computer systems

ECC'11 Proceedings of the 5th European conference on European computing conference
F2BFLY: an on-chip free-space optical network with wavelength-switching

Proceedings of the international conference on Supercomputing
Task migration in three-dimensional meshes

The Journal of Supercomputing
Efficient routing implementation in complex systems-on-chip designs

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Automatic verification for deadlock in Networks-on-Chips with adaptive routing and wormhole switching

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Prevention flow-control for low latency torus Networks-on-Chip

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Non-existence of bipartite graphs of diameter at least 4 and defect 2

Journal of Algebraic Combinatorics: An International Journal
Cluster-based application mapping method for Network-on-Chip

Advances in Engineering Software
Performance evaluation of a wormhole-routed algorithm for irregular mesh NoC interconnect

ICDCN'10 Proceedings of the 11th international conference on Distributed computing and networking
Towards predictable datacenter networks

Proceedings of the ACM SIGCOMM 2011 conference
Communication performance of a recirculative omega high-speed system area network for HPC

Proceedings of the 12th International Conference on Computer Systems and Technologies
Process variation-aware routing in NoC based multicores

Proceedings of the 48th Design Automation Conference
OBQA: Smart and cost-efficient queue scheme for Head-of-Line blocking elimination in fat-trees

Journal of Parallel and Distributed Computing
Virtual path implementation of multi-stream routing in network on chip

PaCT'11 Proceedings of the 11th international conference on Parallel computing technologies
Latency and saturation in networks with finite buffers

Proceedings of the 14th Communications and Networking Symposium
Preference-based multi-objective evolutionary algorithms for power-aware application mapping on NoC platforms

Expert Systems with Applications: An International Journal
Energy characteristic of a processor allocator and a network-on-chip

International Journal of Applied Mathematics and Computer Science - SPECIAL SECTION: Efficient Resource Management for Grid-Enabled Applications
Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures

ACM Transactions on Design Automation of Electronic Systems (TODAES)
On bipartite graphs of defect at most 4

Discrete Applied Mathematics
Editing graphs to satisfy degree constraints: A parameterized approach

Journal of Computer and System Sciences
sFtree: A fully connected and deadlock-free switch-to-switch routing algorithm for fat-trees

ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Stochastic communication for application-specific Networks-on-Chip

The Journal of Supercomputing
Analytical modeling and comparison of fault-tolerant message flow control mechanisms in torus-connected networks

The Journal of Supercomputing
Entropy throttling: a physical approach for maximizing packet mobility in interconnection networks

ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Clustering multicast on hypercube network

HPCC'06 Proceedings of the Second international conference on High Performance Computing and Communications
On high performance multicast algorithms for interconnection networks

HPCC'06 Proceedings of the Second international conference on High Performance Computing and Communications
QoS support for video transmission in high-speed interconnects

HPCC'06 Proceedings of the Second international conference on High Performance Computing and Communications
Preserving the independence of flows in general topologies using turn-prohibition

IWQoS'05 Proceedings of the 13th international conference on Quality of Service
Evolutionary design of group communication schedules for interconnection networks

ISCIS'05 Proceedings of the 20th international conference on Computer and Information Sciences
A novel graceful degradable routing algorithm for 3D on-chip networks

Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
A highly robust distributed fault-tolerant routing algorithm for NoCs with localized rerouting

Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
Evolutionary design of OAB and AAB communication schedules for interconnection networks

EuroGP'06 Proceedings of the 2006 international conference on Applications of Evolutionary Computing
On a deadlock and performance analysis of ALBR and DAR algorithm on X-Torus topology by optimal utilization of Cross Links and minimal lookups

The Journal of Supercomputing
Dynamic evolution of congestion trees: analysis and impact on switch architecture

HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
X-torus: a variation of torus topology with lower diameter and larger bisection width

ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part V
Application-aware deadlock-free oblivious routing based on extended turn-model

Proceedings of the International Conference on Computer-Aided Design
A model for the development of AS fabric management protocols

Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
On the influence of the selection function on the performance of fat-trees

Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
Simple deadlock-free dynamic network reconfiguration

HiPC'04 Proceedings of the 11th international conference on High Performance Computing
Choice of inner switching mechanisms in terabit router

ICN'05 Proceedings of the 4th international conference on Networking - Volume Part I
Visualization of simulation results for the PERCS Hub chip performance verification

Proceedings of the 4th International ICST Conference on Simulation Tools and Techniques
A formal proof of a necessary and sufficient condition for deadlock-free adaptive networks

ITP'10 Proceedings of the First international conference on Interactive Theorem Proving
Development process for clusters on a reconfigurable chip

Computers and Electrical Engineering
Intelligent on/off dynamic link management for on-chip networks

Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Reconfigurable multicore architecture for dynamic processor reallocation

ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
An accurate mathematical performance model of partially adaptive routing in binary n-cube multiprocessors

Mathematical and Computer Modelling: An International Journal
Improvements to the structural simulation toolkit

Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques
A single-cycle output buffered router with layered switching for Networks-on-Chips

Computers and Electrical Engineering
Performance evaluation and design trade-offs for wireless network-on-chip architectures

ACM Journal on Emerging Technologies in Computing Systems (JETC)
An efficient routing technique for mesh-of-tree-based NoC and its performance comparison

International Journal of High Performance Systems Architecture
Tide: An effective and practical design for hierarchical-structured P2P model

Computer Communications
Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers

Neural Networks
Bisection (band)width of product networks with application to data centers

TAMC'12 Proceedings of the 9th Annual international conference on Theory and Applications of Models of Computation
Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method

Microprocessors & Microsystems
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router

Microprocessors & Microsystems
Performance analysis and comparison of 2×4 network on chip topology

Microprocessors & Microsystems
Formal verification methodology considerations for network on chips

Proceedings of the International Conference on Advances in Computing, Communications and Informatics
ACO-Based static routing for network-on-chips

ICCSA'12 Proceedings of the 12th international conference on Computational Science and Its Applications - Volume Part I
An efficient routing methodology to tolerate static and dynamic faults in 2-D mesh networks-on-chip

Microprocessors & Microsystems
Performance modeling of wormhole hypermeshes under hotspot traffic

CSR'07 Proceedings of the Second international conference on Computer Science: theory and applications
Power consumption and performance analysis of 3D NoCs

ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
An efficient fault-tolerant routing methodology for fat-tree interconnection networks

ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications
Design and analysis of multicast communication in multidimensional mesh networks

ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications
A new load balanced routing algorithm for torus networks

ESCAPE'07 Proceedings of the First international conference on Combinatorics, Algorithms, Probabilistic and Experimental Methodologies
Power-aware fat-tree networks using on/off links

HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
Improving a fault-tolerant routing algorithm using detailed traffic analysis

HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
Towards an efficient fat-tree like topology

Euro-Par'12 Proceedings of the 18th international conference on Parallel Processing
Network-on-chip traffic modeling for data flow applications

Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Routing for applications in NoC using ACO-based algorithms

Applied Soft Computing
A source-synchronous Htree-based network-on-chip

Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Exploring topologies for source-synchronous ring-based network-on-chip

Proceedings of the Conference on Design, Automation and Test in Europe
CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems

Proceedings of the Conference on Design, Automation and Test in Europe
An analytical latency model for networks-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Complex network-enabled robust wireless network-on-chip architectures

ACM Journal on Emerging Technologies in Computing Systems (JETC)
CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Scalable progress verification in credit-based flow-control systems

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A fast, source-synchronous ring-based network-on-chip design

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Obtaining the optimal configuration of high-radix Combined switches

Journal of Parallel and Distributed Computing
Congestion-aware ant colony based routing algorithms for efficient application execution on Network-on-Chip platform

Expert Systems with Applications: An International Journal
Scalable high-radix router microarchitecture using a network switch organization

ACM Transactions on Architecture and Code Optimization (TACO)
Message broadcasting via a new fault tolerant irregular advance omega network in faulty and nonfaulty network environments

Journal of Electrical and Computer Engineering
Implementing an interconnection network based on crossbar topology for parallel applications in MPSoC

ICCSA'13 Proceedings of the 13th international conference on Computational Science and Its Applications - Volume 1
Making the network scalable: inter-subnet routing in infiniband

Euro-Par'13 Proceedings of the 19th international conference on Parallel Processing
On multicast for dynamic and irregular on-chip networks using dynamic programming method

Proceedings of the Sixth International Workshop on Network on Chip Architectures
An analytical model for on-chip interconnects in multimedia embedded systems

ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
Efficient multicast schemes for 3-D Networks-on-Chip

Journal of Systems Architecture: the EUROMICRO Journal
Analytical performance modeling of shuffle-exchange inspired mesh-based Network-on-Chips

Performance Evaluation
Nonflat surface level pyramid: a high connectivity multidimensional interconnection network

The Journal of Supercomputing
Non-minimal, turn-model based NoC routing

Microprocessors & Microsystems
Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs

Microprocessors & Microsystems
A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure

Computers and Electrical Engineering
A Fault Tolerant Hierarchical Network on Chip Router Architecture

Journal of Electronic Testing: Theory and Applications

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Abstract

From the Publisher:Addresses the challenges and details the basic underlying concepts of interconnection networks. The book's engineering approach considers the issues that designers need to deal with and presents a broad set of practical solutions. Considerable effort is made to establish new and more.