A networks-on-chip emulation/verification framework

Authors:
Peng Liu;Yangfan Liu;Bingjie Xia;Chunchang Xiang;Xiaohang Wang;Kejun Wu;Weidong Wang;Qingdong Yao
Affiliations:
Department of Information Science and Electronic Engineering, Zhejiang University, Yuquan Campus, Hangzhou 310027, China.;Department of Information Science and Electronic Engineering, Zhejiang University, Yuquan Campus, Hangzhou 310027, China.;Department of Information Science and Electronic Engineering, Zhejiang University, Yuquan Campus, Hangzhou 310027, China.;Department of Information Science and Electronic Engineering, Zhejiang University, Yuquan Campus, Hangzhou 310027, China.;Department of Information Science and Electronic Engineering, Zhejiang University, Yuquan Campus, Hangzhou 310027, China.;Department of Information Science and Electronic Engineering, Zhejiang University, Yuquan Campus, Hangzhou 310027, China.;Department of Information Science and Electronic Engineering, Zhejiang University, Yuquan Campus, Hangzhou 310027, China.;Department of Information Science and Electronic Engineering, Zhejiang University, Yuquan Campus, Hangzhou 310027, China
Venue:
International Journal of High Performance Systems Architecture
Year:
2011

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Abstract

The emulation and functional validation are essential to the assessment of the correctness and performance of networks-on-chip architecture. A flexible hardware/software networks-on-chip open platform (NoCOP) emulation framework is designed and implemented for exploring the on-chip interconnection network architectures. An instruction set simulator and universal serial bus communicator control and configure the emulation parameters and process that are running on the host computer as active elements in the emulation framework. The experimental results show that the proposed emulation/verification framework can speed up the simulation, preserve the cycle accuracy and decrease the usage of the resources of field programmable gate array.