VHDL-based simulation environment for Proteo NoC

Authors:
D. Siguenza-Tortosa;J. Nurmi
Affiliations:
IDCS, Tampere Univ. of Technol., Finland;IDCS, Tampere Univ. of Technol., Finland
Venue:
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Year:
2002

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Abstract

The purpose of this paper is to present the work that has been carried out for the creation of a simulation environment of our network-on-chip (NoC) architecture, called "Proteo". In an intellectual property (IP) based design methodology also the interconnection structures may be treated as IPs. The Proteo project is aimed at creating a library of pre-designed communication blocks that can be selected from a component library and configured by automated tools. The network implements packet switching in a hierarchical topology. We have created a high level model of our network in VHDL, allowing mixed-abstraction level simulation of our synthesizable code for validation.