Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Microarchitectural exploration with Liberty
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Network on Chip Simulations for Benchmarking
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
Replacing global wires with an on-chip network: a power analysis
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
VHDL-based simulation environment for Proteo NoC
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
A Power and Energy Exploration of Network-on-Chip Architectures
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
An energy and performance exploration of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high level power model for Network-on-Chip (NoC) router
Computers and Electrical Engineering
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This paper presents a system-level Network-on-Chip simulation platform integrating the transaction-level performance model of NoC components and their architecture-level energy models. The transaction-level model written in SystemC enables fast simulation speed and the architectural energy model estimates communication energy, including both dynamic and leakage, dissipating on routers and links through the transaction-level simulation. This power model supports temporal power profiling for each NoC component and spatial power snapshots for the whole NoC, making it easy to inspect the power implications under application workloads. Applying this energy model on 8 deep sub-micron CMOS processes from 180nm to 45nm, we reveal an average 2.8X leakage power increase for each technology evolution. With temporal and spatial profiling for burst-mode applications, the power hungry portions in both time- and space-domains can be identified, and in turn it provides useful information for the energy-aware NoC design space exploration for the future nanoscale IC technologies.This paper presents a system-level Network-on-Chip simulation platform integrating the transaction-level performance model of NoC components and their architecture-level energy models. The transaction-level model written in SystemC enables fast simulation speed and the architectural energy model estimates communication energy, including both dynamic and leakage, dissipating on routers and links through the transaction-level simulation. This power model supports temporal power profiling for each NoC component and spatial power snapshots for the whole NoC, making it easy to inspect the power implications under application workloads. Applying this energy model on 8 deep sub-micron CMOS processes from 180nm to 45nm, we reveal an average 2.8X leakage power increase for each technology evolution. With temporal and spatial profiling for burst-mode applications, the power hungry portions in both time- and space-domains can be identified, and in turn it provides useful information for the energy-aware NoC design space exploration for the future nanoscale IC technologies.This paper presents a system-level Network-on-Chip simulation platform integrating the transaction-level performance model of NoC components and their architecture-level energy models. The transaction-level model written in SystemC enables fast simulation speed and the architectural energy model estimates communication energy, including both dynamic and leakage, dissipating on routers and links through the transaction-level simulation. This power model supports temporal power profiling for each NoC component and spatial power snapshots for the whole NoC, making it easy to inspect the power implications under application workloads. Applying this energy model on 8 deep sub-micron CMOS processes from 180nm to 45nm, we reveal an average 2.8X leakage power increase for each technology evolution. With temporal and spatial profiling for burst-mode applications, the power hungry portions in both time- and space-domains can be identified, and in turn it provides useful information for the energy-aware NoC design space exploration for the future nanoscale IC technologies.