A Complete Network-On-Chip Emulation Framework
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Fault tolerance overhead in network-on-chip flow control schemes
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
MAIA: a framework for networks on chip generation and verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
NoCEE: energy macro-model extraction methodology for network on chip routers
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
NoC Design and Implementation in 65nm Technology
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Run-time adaptive on-chip communication scheme
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Transaction level model simulator for NoC-based MPSoC platform
IMCAS'07 Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
ADAM: run-time agent-based distributed application mapping for on-chip communication
Proceedings of the 45th annual Design Automation Conference
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
NeuroNoC: neural network inspired runtime adaptation for an on-chip communication architecture
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Cooperative template mechanism for cooperative design
CSCWD'05 Proceedings of the 9th international conference on Computer Supported Cooperative Work in Design II
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
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In this paper, we describe NoCGEN, a Network On Chip (NoC)generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularisedrouter components that can be used to form different routerswith a varying number of ports, routing algorithms, data widthsand buffer depths. A graph description representing the inter-connection between these routers is used to generate a top-levelVHDL description.A wormhole output-queued 2-D mesh router was created toverify the capability of NoCGEN. Various parameterized designs were synthesized to provide estimated gate counts of 129Kto 695K for a number of topologies varying from a 2 x 2 meshto a 4x4 mesh, with constant data bus size width of 32. TheNoC was simulated with random traffic using a mixed SystemC/ VHDL environment to ensure correctness of operation and toobtain performance and average latency. The results show anaccepted load of 53% to 55.6% with an increase in buffer depthfrom 8 to 32 flits for the 4x4 mesh router.