Spidergon STNoC design flow

Authors:
Florentine Dubois;Jose Cano;Marcello Coppola;Jose Flich;Frederic Petrot
Affiliations:
ST Microelectronics, TIMA laboratory, CNRS/Grenoble INP/UJF, Grenoble, France;Universitat Politècnica de València, València, Spain;ST Microelectronics, Grenoble, France;Universitat Politècnica de València, València, Spain;TIMA laboratory, CNRS/Grenoble INP/UJF, Grenoble, France
Venue:
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Year:
2011

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Abstract

In this demonstration we present an enhanced version of the usual Spidergon STNoC design flow. In addition, we show the automatic generation of a simulation platform that can be used to perform early architecture exploration.