Data networks
Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
A comprehensive analytical model for wormhole routing in multicomputer systems
Journal of Parallel and Distributed Computing
An Analytical Model of Adaptive Wormhole Routing in Hypercubes in the Presence of Hot Spot Traffic
IEEE Transactions on Parallel and Distributed Systems
A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems
Journal of VLSI Signal Processing Systems - Special issue on signal processing systems design and implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Efficient link capacity and QoS design for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis and optimization of prediction-based flow control in networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Proceedings of the 23rd international conference on Supercomputing
Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Power optimization for application-specific networks-on-chips: A topology-based approach
Microprocessors & Microsystems
Performance analysis of small non-uniform packet switches
Performance Evaluation
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An accurate and efficient performance analysis approach based on queuing model for Network on Chip
Proceedings of the 2009 International Conference on Computer-Aided Design
A performance analytical model for Network-on-Chip with constant service time routers
Proceedings of the 2009 International Conference on Computer-Aided Design
Throughput-oriented NoC topology generation and analysis for high performance SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A modeling tool for simulating and design of on-chip network systems
Microprocessors & Microsystems
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Network-on-Chip Architectures for Neural Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Modeling and analysis of PC-based software routers
Computer Communications
Performance modeling of n-dimensional mesh networks
Performance Evaluation
Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Application-specific 3D Network-on-Chip design using simulated allocation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Scalable network-on-chip architecture for configurable neural networks
Microprocessors & Microsystems
Static timing analysis for modeling QoS in networks-on-chip
Journal of Parallel and Distributed Computing
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Delay analysis of wormhole based heterogeneous NoC
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Real-time communication analysis for networks with two-stage arbitration
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
System interconnect design exploration for embedded MPSoCs
Proceedings of the System Level Interconnect Prediction Workshop
Optimized 3D Network-on-Chip Design Using Simulated Allocation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Analytical modeling for multi-transaction bus on distributed systems
ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
Efficient genetic based topological mapping using analytical models for on-chip networks
Journal of Computer and System Sciences
Hi-index | 0.00 |
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. In this paper, we first present a generalized router model and then utilize this novel model for doing NoC performance analysis. The proposed model can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.