A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
A Complete Network-On-Chip Emulation Framework
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Traffic generation and performance evaluation for mesh-based NoCs
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
VHDL-based simulation environment for Proteo NoC
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
A design methodology for application-specific networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
Automatic phase detection for stochastic on-chip traffic generation
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Application - specific NoC platform design based on System Level Optimization
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Analytical router modeling for networks-on-chip performance analysis
Proceedings of the conference on Design, automation and test in Europe
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
Throughput-oriented NoC topology generation and analysis for high performance SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Chip-set for video display of multimedia information
IEEE Transactions on Consumer Electronics
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The conception of Network-on-Chip (NoC) presents system designers with a new approach to the design of on-chip inter-connection structures. However, such networks present designers with a large number of design parameters and decisions, many of which are critical to the efficient operation of over-all on-chip system. To aid the design process of complex systems-on-chip, this paper presents a NoC simulation environment that has been developed and implemented using the SystemC transaction-level modeling language. The simulation environment consists of on-chip components as well as traffic generators, which can generate various types of traffic patterns. The simulation environment has also been integrated with the NoC topology generation tool being developed in our group. A set of simulation results demonstrates the types of parameters that can affect the performance of on-chip systems, including topology variations, network latency and achievable throughput. These results also verify the modeling capabilities of the proposed simulation environment.