Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Networks on chip
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
OCCN: A Network-On-Chip Modeling and Simulation Framework
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A topology design customization approach for STNoC
Proceedings of the 2nd international conference on Nano-Networks
Application-specific networks-on-chip topology customization using network partitioning
IFMT '08 Proceedings of the 1st international forum on Next-generation multicore/manycore technologies
Proceedings of the 2nd International Conference on Simulation Tools and Techniques
Contention-free on-chip routing of optical packets
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Evaluating the energy consumption and the silicon area of on-chip interconnect architectures
Journal of Systems Architecture: the EUROMICRO Journal
An analytical performance model for the Spidergon NoC with virtual channels
Journal of Systems Architecture: the EUROMICRO Journal
A modeling tool for simulating and design of on-chip network systems
Microprocessors & Microsystems
The connection-then-credit flow control protocol for heterogeneous multicore systems-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
aEqualized: a novel routing algorithm for the Spidergon network on chip
Proceedings of the Conference on Design, Automation and Test in Europe
A methodology for design of unbuffered router microarchitecture for S-mesh NoC
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Hierarchical opto-electrical on-chip network for future multiprocessor architectures
Journal of Systems Architecture: the EUROMICRO Journal
Computers and Electrical Engineering
Scalable architecture for a contention-free optical network on-chip
Journal of Parallel and Distributed Computing
Semi-serial on-chip link implementation for energy efficiency and high throughput
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards a scalable, low-power all-optical architecture for networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simulation-based analysis of some recent architectures for Network on Chip (NoC). Specifically, the Ring, Spidergon and 2D Mesh NoC topologies have been compared, both under uniform load and under more realistic load assumptions in the SoC domain. The main performance indexes considered are NoC throughput and latency, as a function of variable data-injection rates, source and destination distributions, variable number of nodes. Results show that the Spidergon topology is a good trade-off between performance, scalability of the most efficient architectures inherited from the parallel computing systems design, constraints about simple management, small energy and area requirements for SoCs.