Parallel computing: theory and comparisons
Parallel computing: theory and comparisons
Performance Evaluation of Switch-Based Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
VLSI Architecture: Past, Present, and Future
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
A Fault-Tolerant FPGA-based Multi-Stage Interconnection Network for Space Applications
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Performance Analysis of Network Architectures
Performance Analysis of Network Architectures
Hierarchical Network-on-Chip for Embedded Many-Core Architectures
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
| Hi-index | 0.00 |
Performance of two network-on-chip (NoC) topologies is compared for the use in multicore processors. The performance evaluation is supported by the CINSim simulator. This simulator has been developed to model a variety of network topologies that are based on atomic components such as buffers, routers, traffic generators, and target buffers. The development of this simulator was driven by the investigation of networks-on-chip. But off-chip networks can be examined as well. Two examples for NoC topologies, a mesh and a bidirectional interconnection network, are compared. Unicast traffic is used as well as multicast and local traffic, which both represent a significant part of the network traffic for evaluating multi-core processors. In addition to the performance, the mean distance, the diameter, and the buffer cost are calculated for both network topologies. The results show that bidirectional multistage interconnection networks outperform meshes. A clearly better scalability is shown by the bidirectional multistage interconnection networks.