Communications of the ACM - Special section on computer architecture
An evaluation of directory schemes for cache coherence
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
The design of the Caltech Mosaic C multicomputer
Proceedings of the 1993 symposium on Research on integrated systems
The J-machine multicomputer: an architectural evaluation
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Proceedings of the 28th annual international symposium on Microarchitecture
Synchronization and communication in the T3E multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Proceedings of the 24th annual international symposium on Computer architecture
Active pages: a computation model for intelligent memory
Proceedings of the 25th annual international symposium on Computer architecture
Exploiting fine-grain thread level parallelism on the MIT multi-ALU processor
Proceedings of the 25th annual international symposium on Computer architecture
Communications of the ACM - Special issue on computer architecture
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
A Case for NOW (Networks of Workstations)
IEEE Micro
IEEE Transactions on Parallel and Distributed Systems
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
A no-busy-wait balanced tree parallel algorithmic paradigm
Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures
VLSI layout and packaging of butterfly networks
Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures
Experiments with list ranking for explicit multi-threaded (XMT) instruction parallelism
Journal of Experimental Algorithmics (JEA)
Systolic Opportunities for Multidimensional Data Streams
IEEE Transactions on Parallel and Distributed Systems
Coping with Latency in SOC Design
IEEE Micro
Experiments with List Ranking for Explicit Multi-Threaded (XMT) Instruction Parallelism
WAE '99 Proceedings of the 3rd International Workshop on Algorithm Engineering
Multilayer VLSI Layout for Interconnection Networks
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
SCMP: a single-chip message-passing parallel computer
The Journal of Supercomputing - Special issue: Parallel and distributed processing and applications
SHAPES:: a tiled scalable software hardware architecture platform for embedded systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Platform-based resource binding using a distributed register-file microarchitecture
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
MLMIN: A multicore processor and parallel computer network topology for multicast
Computers and Operations Research
Utilizing shared data in chip multiprocessors with the Nahalal architecture
Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
FPGA implementation of real-time skin color detection with mean-based surface flattening
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2nd International Conference on Simulation Tools and Techniques
Networks on Chips: from research to products
Proceedings of the 47th Design Automation Conference
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This paper examines the impact of VLSI technology on the evolution of Computer Architecture and Projects the future of this evolution. We see that over the past 20 years, the increased density of VLSI chips was applied to close the gap between microprocessors and high-end CPUs. Today this gap is fully closed and adding devices to uniprocessors is well beyond the point of diminishing returns. To continue to convert the increasing density of VLSI to computer performance we see little alternative to building multicomputers. We sketch the architecture of a VLSI multicomputer constructed from c. 2009 processor-DRAM chips and outline some of the challenges involved in building such a system. We suggest that the software transition from sequential processors to such fine-grain multicomputers can be eased by using the multicomputer as the memory system of a conventional computer.