VLSI on-chip interconnection performance simulations and measurements
IBM Journal of Research and Development
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Interconnect resource-aware placement for hierarchical FPGAs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Connectivity Models for Optoelectronic Computing Systems
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning
ALENEX '99 Selected papers from the International Workshop on Algorithm Engineering and Experimentation
RTL Estimation of Steering Logic Power
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Balancing Logic Utilization and Area Efficiency in FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Very Large Scale Spatial Computing
UMC '02 Proceedings of the Third International Conference on Unconventional Models of Computation
VLSI Architecture: Past, Present, and Future
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
ALMS: Automated logic mapping system
DAC '71 Proceedings of the 8th Design Automation Workshop
Refinements of Rent's Rule Allowing Accurate Interconnect Complexity Modeling
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Teramac-configurable custom computing
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A novel net-degree distribution model and its application to floorplanning benchmark generation
Integration, the VLSI Journal
IEEE Transactions on Computers
Impact of the LSI on High-Speed Computer Packaging
IEEE Transactions on Computers
Buffering global interconnects in structured ASIC design
Integration, the VLSI Journal
Efficient tiling patterns for reconfigurable gate arrays
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Efficient tiling patterns for reconfigurable gate arrays
Proceedings of the 2008 international workshop on System level interconnect prediction
The next resource war: computation vs. communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Rent's rule and parallel programs: characterizing network traffic behavior
Proceedings of the 2008 international workshop on System level interconnect prediction
Efficient tree topology for FPGA interconnect network
Proceedings of the 18th ACM Great Lakes symposium on VLSI
On the trade-off between power and flexibility of FPGA clock networks
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A Network of Time-Division Multiplexed Wiring for FPGAs
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Wirelength modeling for homogeneous and heterogeneous FPGA architectural development
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
High-performance, cost-effective heterogeneous 3D FPGA architectures
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
High-performance, cost-effective heterogeneous 3D FPGA architectures
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Post-placement interconnect entropy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Using circuit structural analysis techniques for networks in systems biology
Proceedings of the 11th international workshop on System level interconnect prediction
A pre-placement net length estimation technique for mixed-size circuits
Proceedings of the 11th international workshop on System level interconnect prediction
From 3D circuit technologies and data structures to interconnect prediction
Proceedings of the 11th international workshop on System level interconnect prediction
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Proceedings of the 11th international workshop on System level interconnect prediction
Equivalence of memory to "Random Logic"
IBM Journal of Research and Development
Wire length distribution for placements of computer logic
IBM Journal of Research and Development
Electronic packaging evolution in IBM
IBM Journal of Research and Development
Influence on LSI package wireability of via availability and wiring track accessibility
IBM Journal of Research and Development
Lead reduction among combinatorial logic circuit
IBM Journal of Research and Development
Interconnect opportunities for gigascale integration
IBM Journal of Research and Development
Towards scalable placement for FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
FPGA interconnect topologies exploration
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Information flow and interconnections in computing: extensions and applications of Rent's rule
Journal of Parallel and Distributed Computing
Fast, accurate a priori routing delay estimation
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cost-aware three-dimensional (3D) many-core multiprocessor design
Proceedings of the 47th Design Automation Conference
FPGA architecture optimisation using geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VLSI design optimization of input/output-buffered broadband ATM switches
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 2
Fabrication cost analysis and cost-aware design space exploration for 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A pre-placement individual net length estimation model and an application for modern circuits
Integration, the VLSI Journal
Cut-demand based routing resource allocation and consolidation for routability enhancement
Proceedings of the 16th Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Comparison between heterogeneous mesh-based and tree-based application specific FPGA
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Exploration of heterogeneous FPGA architectures
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Pinned to the walls: impact of packaging and application properties on the memory and power walls
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Spatial hardware implementation for sparse graph algorithms in GraphStep
ACM Transactions on Autonomous and Adaptive Systems (TAAS)
Toward five-dimensional scaling: how density improves efficiency in future computers
IBM Journal of Research and Development
Toward PDN resource estimation: a law of general power density
Proceedings of the System Level Interconnect Prediction Workshop
Construction of realistic gate sizing benchmarks with known optimal solutions
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
On two-layer brain-inspired hierarchical topologies – a rent's rule approach –
Transactions on High-Performance Embedded Architectures and Compilers IV
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Implications of electronics technology trends to algorithm design
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
On the asymptotic costs of multiplexer-based reconfigurability
Proceedings of the 49th Annual Design Automation Conference
Can pin access limit the footprint scaling?
Proceedings of the 49th Annual Design Automation Conference
Handling global traffic in future CMP NoCs
Proceedings of the International Workshop on System Level Interconnect Prediction
Microprocessors & Microsystems
L24: Parallelism, performance, energy efficiency, and cost trade-offs in future sensor platforms
ACM Transactions on Embedded Computing Systems (TECS)
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Rent's rule based FPGA packing for routability optimization
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Quantifying the cost and benefit of latency insensitive communication on FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA
Microelectronics Journal
| Hi-index | 14.99 |
Partitions of the set of blocks of a computer logic graph, also called a block graph, into subsets called modules demonstrate that a two-region relationship exists between P, the average number of pins per module, and B, the average number of blocks per module. In the first region, P = KBr, where K is the average number of pins per block and 0.57 = r = 0.75. In the second region, that is, where the number of modules is small (i.e., 1-5), P is less than predicted by the above formula and is given by a more complex relationship. These conclusions resulted from controlled partitioning experiments performed using a computer program to partition four logic graphs varying in size from 500 to 13 000 circuits representing three different computers. The size of a block varied from one NOR circuit in one of the block graphs to a 30-circuit chip in one of the other block graphs.