A justification of, and an improvement on, a useful rule for predicting circuit-to-pin ratios
DAC '69 Proceedings of the 6th annual Design Automation Conference
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Equivalence of memory to "Random Logic"
IBM Journal of Research and Development
Wire length distribution for placements of computer logic
IBM Journal of Research and Development
Provably good routing in graphs: regular arrays
STOC '85 Proceedings of the seventeenth annual ACM symposium on Theory of computing
Connectivity Models for Optoelectronic Computing Systems
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
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HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Modeling routing demand for early-stage FPGA architecture development
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Wirelength modeling for homogeneous and heterogeneous FPGA architectural development
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
A pre-placement net length estimation technique for mixed-size circuits
Proceedings of the 11th international workshop on System level interconnect prediction
A framework for core-level modeling and design of reconfigurable computing algorithms
Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Information flow and interconnections in computing: extensions and applications of Rent's rule
Journal of Parallel and Distributed Computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA architecture optimisation using geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A pre-placement individual net length estimation model and an application for modern circuits
Integration, the VLSI Journal
Effect of the prefabricated routing track distribution on FPGA area-efficiency
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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This paper develops a relation between the partitioning properties of computer logic and the distribution of connection lengths. The computation of length distributions is important for wirability analysis and delay estimation. The principal result is that an exponential partitioning function leads to an inverse power law length distribution.