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DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-energy embedded FPGA structures
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
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ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
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Proceedings of the conference on Design, automation and test in Europe
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FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
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Architecture and CAD for Deep-Submicron FPGAs
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FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
An Overview of the COBRA-ABS High Level Synthesis System for Multi-FPGA Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
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Proceedings of the 2003 international symposium on Low power electronics and design
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Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Elements of discrete mathematics (McGraw-Hill computer science series)
Elements of discrete mathematics (McGraw-Hill computer science series)
IEEE Transactions on Computers
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Power modeling and characteristics of field programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation
Proceedings of the 46th Annual Design Automation Conference
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Foundations and Trends in Electronic Design Automation
FPGA latency optimization using system-level transformations and DFG restructuring
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. LOPASS includes three major components: 1) a flexible high-level power estimator for FPGAs considering the power consumption of various FPGA logic components and interconnects; 2) a simulated-annealing optimization engine that carries out resource selection and allocation, scheduling, functional unit binding, register binding, and interconnection estimation simultaneously to reduce power effectively; and 3) a k-cofamily-based register binding algorithm and an efficient port assignment algorithm that reduce interconnections in the data path through multiplexer optimization. The experimental results show that LOPASS produces promising results on latency optimization compared to an academic high-level synthesis tool SPARK. Compared to an early commercial high-level synthesis tool, namely, Synopsys Behavioral Compiler, LOPASS is 61.6% better on power consumption and 10.6% better on clock period on average. Compared to a current commercial tool, namely, Impulse C, LOPASS is 31.1% better on power reduction with an 11.8% penalty on clock period.