Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power estimation of cell-based CMOS circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Register-transfer level estimation techniques for switching activity and power consumption
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Fast high-level power estimation for control-flow intensive design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
IMPACT: a high-level synthesis system for low power control-flow intensive circuits
Proceedings of the conference on Design, automation and test in Europe
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems
IEEE Design & Test
Optimizing Power in ASIC Behavioral Synthesis
IEEE Design & Test
Accurate high level datapath power estimation
EDTC '97 Proceedings of the 1997 European conference on Design and Test
SCALP: an iterative-improvement-based low-power data path synthesis system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power high-level synthesis for FPGA architectures
Proceedings of the 2003 international symposium on Low power electronics and design
Optimal simultaneous module and multivoltage assignment for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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