High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Asynchronous Circuits for Low Power: A DCC Error Corrector
IEEE Design & Test
Power-profiler: optimizing ASICs power consumption at the behavioral level
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Low Power Digital CMOS Design
Power Aware Design Methodologies
Power Aware Design Methodologies
Algorithms for High-Level Synthesis
IEEE Design & Test
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Trade-Off Analysis of a Low-Power Image Coding Algorithm
Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design
Efficient switching activity computation during high-level synthesis of control-dominated designs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of a high-throughput low-power IS95 Viterbi decoder
Proceedings of the 39th annual Design Automation Conference
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Behavioral Array Mapping into Multiport Memories Targeting Low Power
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
ILP models for simultaneous energy and transient power minimization during behavioral synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
Design of a low power MPEG-1 motion vector reconstructor
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Design of a 20-Mb/s 256-state viterbi decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
This article provides a tutorial survey of architectures of commercially available high-capacity field-programmable devices (FPDs), and gives a summary of recent research results in the field. In the survey section, we first define the relevant terminology in the field and then describe the recent evolution of FPDs. The three main categories of FPDs are delineated: Simple PLDs (SPLDs), Complex PLDs (CPLDs) and Field-Programmable Gate Arrays (FPGAs). We then give details of the architectures of all of the most important commercially available chips. The second part of the article gives an overview of the most important research results on FPD architecture over the past six years, and provides suggestions as to features that may be included in future architectures.