Syntax-directed translation of concurrent programs into self-timed circuits
Proceedings of the fifth MIT conference on Advanced research in VLSI
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Communicating sequential processes
Communications of the ACM
Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
The VLSI-programming language tangram and its translation into handshake circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Occam Programming Manual
Estimation and bounding of energy consumption in burst-mode control circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Concurrency-oriented optimization for low-power asynchronous systems
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The tangram framework (embedded tutorial): asynchronous circuits for low power
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test
Journal of Electronic Testing: Theory and Applications
Optimizing Power in ASIC Behavioral Synthesis
IEEE Design & Test
Statistical Carry Lookahead Adders
IEEE Transactions on Computers
Asynchronous Comparison-Based Decoders for Delay-Insensitive Codes
IEEE Transactions on Computers
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
A New Methodology to Design Low-Power Asynchronous Circuits
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Testing self-timed circuits using partial scan
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Stretching quasi delay insensitivity by means of extended isochronic forks
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A single-rail re-implementation of a DCC error detector using a generic standard-cell library
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Single-rail handshake circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
High-level test evaluation of asynchronous circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
New CMOS VLSI linear self-timed architectures
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A Low-power Asynchronous Data-path for a FIR Filter Bank
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Optimizing average-case delay in technology mapping of burst-mode circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous Microengines for Efficient High-level Control
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Limitations of VLSI implementation of delay-insensitive codes
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Synchronous Test Generation Model for Asynchronous Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Critical hazard free test generation for asynchronous circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
5.2 Self-Timed Boundary-Scan Cells for Multi-Chip Module Test
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Power reduction of asynchronous logic circuits using activity detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architectural optimization for low-power nonpipelined asynchronous systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The authors describe a complete low-power digital compact cassette error corrector. Using Tangram, a high-level programming language, they designed two asynchronous circuits that correct errors on DCC specifications.