Communications of the ACM
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Testing delay-insensitive circuits
Testing delay-insensitive circuits
Translating concurrent communicating programs into asynchronous circuits
Translating concurrent communicating programs into asynchronous circuits
Asynchronous Circuits for Low Power: A DCC Error Corrector
IEEE Design & Test
Testing two-phase transition signaling based self-timed circuits in a synthesis environment
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
Automatic Synthesis of Fast Compact Asynchronous Control Circuits
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
Testing Delay-Insensitive Circuits
Testing Delay-Insensitive Circuits
Automatic generation of synchronous test patterns for asynchronous circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Formal Asynchronous Systems Modelling
Fundamenta Informaticae
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This paper presents a partial scan method for testing both the control and data path parts of macromodule based self-timed circuits for stuck-at faults. Compared with other proposed test methods for testing control paths in self-timed circuits, this technique offers better fault coverage under a stuck-at input model than methods using self-checking properties, and requires fewer storage elements to be made scannable than full scan approaches with similar fault coverage. A new method is proposed to test the sequential network in the control path in this partial scan environment. The partial scan approach has also been applied to data paths, where structural analysis is used to select which latches should be made scannable to break cycles in the circuit. Experimental data is presented to show that high fault coverage is possible using this method with only a subset of storage elements in the control and data paths being made scannable.