Digital logic testing and simulation
Digital logic testing and simulation
Theory and Design Switching Circ
Theory and Design Switching Circ
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Designing Circuits with Partial Scan
IEEE Design & Test
On the over-specification problem in sequential ATPG algorithms
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
SIESTA: a multi-facet scan design system
EURO-DAC '92 Proceedings of the conference on European design automation
DAC '93 Proceedings of the 30th international Design Automation Conference
A cost-based approach to partial scan
DAC '93 Proceedings of the 30th international Design Automation Conference
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Design for testability for path delay faults in sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Selective pseudo scan: combinational ATPG with reduced scan in a full custom RISC microprocessor
DAC '93 Proceedings of the 30th international Design Automation Conference
Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Selecting partial scan flip-flops for circuit partitioning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Resynthesis and retiming for optimum partial scan
DAC '94 Proceedings of the 31st annual Design Automation Conference
Optimizing resource utilization and testability using hot potato techniques
DAC '94 Proceedings of the 31st annual Design Automation Conference
Testability analysis and improvement from VHDL behavioral specifications
EURO-DAC '94 Proceedings of the conference on European design automation
Partial scan with pre-selected scan signals
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Partial scan selection for user-specified fault coverage
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Test register insertion with minimum hardware cost
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Cost-free scan: a low-overhead scan path design methodology
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A controller-based design-for-testability technique for controller-data path circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computers
Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Layout driven selecting and chaining of partial scan flip-flops
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Test point insertion: scan paths through combinational logic
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Partial scan design based on circuit state information
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Identification of unsettable flip-flops for partial scan and faster ATPG
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Functional design for testability of control-dominated architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Exploiting hardware sharing in high-level synthesis for partial scan optimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Improving Testability of Non-Scan Designs during BehavioralSynthesis
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
A test synthesis approach to reducing BALLAST DFT overhead
DAC '97 Proceedings of the 34th annual Design Automation Conference
Partial scan delay fault testing of asynchronous circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Layout Driven Selection and Chaining of Partial Scan Flip-Flops
Journal of Electronic Testing: Theory and Applications
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Controller Resynthesis for Testability Enhancement of RTLController/Data Path Circuits
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Configuring multiple scan chains for minimum test time
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Test generation for delay faults in non-scan and partial scan sequential circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Full scan fault coverage with partial scan
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Incremental Testability Analysis for Partial Scan Selection and Design Transformations
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Partial Scan with Preselected Scan Signals
IEEE Transactions on Computers
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
Partial BIST insertion to eliminate data correlation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Deterministic BIST with Partial Scan
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
A New Class of Sequential Circuits with Combinational Test Generation Complexity
IEEE Transactions on Computers
Proceedings of the conference on Design, automation and test in Europe
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Generating efficient tests for continuous scan
Proceedings of the 38th annual Design Automation Conference
Low-cost sequential ATPG with clock-control DFT
Proceedings of the 39th annual Design Automation Conference
Test generation for acyclic sequential circuits with hold registers
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Partial Scan Testing on the Register-Transfer Level
Journal of Electronic Testing: Theory and Applications
Economic Effects in Design and Test
IEEE Design & Test
IEEE Design & Test
IEEE Design & Test
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
Performance Analysis of Asynchronous Circuits Using Markov Chains
Concurrency and Hardware Design, Advances in Petri Nets
A novel combinational testability analysis by considering signal correlation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An almost full-scan BIST solution-higher fault coverage and shorter test application time
ITC '98 Proceedings of the 1998 IEEE International Test Conference
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Design-for-Verification Technique for Functional Pattern Reduction
IEEE Design & Test
Testable design of non-scan sequential circuits using extra logic
ATS '95 Proceedings of the 4th Asian Test Symposium
Test sequence compaction by reduced scan shift and retiming
ATS '95 Proceedings of the 4th Asian Test Symposium
A STAFAN-like functional testability measure for register-level circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Testing self-timed circuits using partial scan
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Partial Scan High-Level Synthesis
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Fault diagnosis using state information
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Partial scan design for technology mapped circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Genetic Algorithms for Scan Path Design
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Design for high-speed testability of stuck-at faults
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Retiming with logic duplication transformation: theory and an application to partial scan
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Sequential Circuit Testing: From DFT to SFT
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Synthesis for Testability by Two-Clock Control
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Deriving Signal Constraints to Accelerate Sequential Test Generation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Multiple Faults: Modeling, Simulation and Test
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Testing High Speed VLSI Devices Using Slower Testers
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Partial Scan Using Multi-Hop State Reachability Analysis
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
At-Speed Logic BIST Using a Frozen Clock Testing Strategy
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Combinational Test Generation for Various Classes of Acyclic Sequential Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs
ITC '97 Proceedings of the 1997 IEEE International Test Conference
SCAN SYNTHESIS FOR ONE-HOT SIGNALS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ACT: A DFT Tool for Self-Timed Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution
IEEE Transactions on Computers
A synthesis-for-transparency approach for hierarchical and system-on-a-chip test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
Fast Computation of Data Correlation Using BDDs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reduced Test Application Time Based on Reachability Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Using a software testing technique to identify registers for partial scan implementation
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Initialization-based test pattern generation for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transforming behavioral specifications to facilitate synthesis of testable designs
ITC'94 Proceedings of the 1994 international conference on Test
ATPG for heat dissipation minimization during test application
ITC'94 Proceedings of the 1994 international conference on Test
Reduced scan shift: a new testing method for sequential circuits
ITC'94 Proceedings of the 1994 international conference on Test
Do you practice safe test? what we found out about your habits
ITC'94 Proceedings of the 1994 international conference on Test
Configuring flip-flops to BIST registers
ITC'94 Proceedings of the 1994 international conference on Test
A novel automatic test pattern generator for asynchronous sequential digital circuits
Microelectronics Journal
Eliminating the Timing Penalty of Scan
Journal of Electronic Testing: Theory and Applications
| Hi-index | 15.00 |
A method of partial scan design is presented in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit. Experimental data are given to show that the test generation complexity may grow exponentially with the length of the cycles in the circuit. This complexity grows only linearly with the sequential depth. Graph-theoretic algorithms are presented to select a minimal set of flip-flops for eliminating cycles and reducing the sequential depth. Tests for the resulting circuit are generated by a sequential logic test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequence produced by the test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequences produced by the test generator. 98% fault coverage is obtained for a 5000-gate circuit by scanning just 5% of the flip-flops.