Logic design of digital systems
Logic design of digital systems
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
On the generation of test patterns for multiple faults
Journal of Electronic Testing: Theory and Applications
System Test and Diagnosis
Generating Tests for Delay Faults in Nonscan Circuits
IEEE Design & Test
Combinational test generation for various classes of acyclic sequential circuits
Proceedings of the IEEE International Test Conference 2001
Combinational Test Generation for Acyclic Sequential Circuits using a Balanced ATPG Model
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Exclusive Test and its Applications to Fault Diagnosis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Simplifying diagnosis using LSAT: a propositional approach to reasoning from first principles
CPAIOR'05 Proceedings of the Second international conference on Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems
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We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most n+3 modeling gates, when the multiplicity of the targeted fault is n. We prove that the modeled circuit is functionally equivalent to the original circuit and the targeted multiple fault is equivalent to the modeled single stuck-at fault. The technique allows simulation and test generation for any arbitrary multiple fault in combinational or sequential circuits. We further demonstrate applications to bridging-fault modeling, diagnosis, circuit optimization, and testing of multiply-testable faults. The modeling technique has an additional application in a recently published combinational ATPG method for partial-scan circuits in which some lines are split, leading to a transformation of single stuck-at faults into multiple faults.