Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits
EURO-DAC '92 Proceedings of the conference on European design automation
A method of delay fault test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Syndrome-Based Functional Delay Fault Location in Linear Digital Data-Flow Graphs
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
An efficient path delay fault coverage estimator
DAC '94 Proceedings of the 31st annual Design Automation Conference
Functional test generation for path delay faults
ATS '95 Proceedings of the 4th Asian Test Symposium
Sequential logic path delay test generation by symbolic analysis
ATS '95 Proceedings of the 4th Asian Test Symposium
Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Multiple Faults: Modeling, Simulation and Test
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Effects of Multi-cycle Sensitization on Delay Tests
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Novel Solution for Chip-Level Functional Timing Verification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Testing High Speed VLSI Devices Using Slower Testers
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
ITC '01 Proceedings of the 2001 IEEE International Test Conference
On path delay testing in a standard scan environment
ITC'94 Proceedings of the 1994 international conference on Test
| Hi-index | 0.00 |
A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing.