At-speed delay testing of synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Generation of high quality non-robust tests for path delay faults
DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient branch and bound search with application to computer-aided design
Efficient branch and bound search with application to computer-aided design
Generating Tests for Delay Faults in Nonscan Circuits
IEEE Design & Test
Sequential logic path delay test generation by symbolic analysis
ATS '95 Proceedings of the 4th Asian Test Symposium
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Effective Path Selection for Delay Fault Testing of Sequential Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
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We present a new test generator for path delay faults in sequential circuits to generate validatable non-robust (VNR) tests. We use Boolean flags to generate VNR tests dynamically during the generation of robust tests, by relaxing certain off-path input requirements to those of non-robust tests. Results show that VNR tests provide a 10% improvement over the robust coverage of path delay faults in the sequential circuits considered. We adopt a 13-valued algebra to generate robust tests with hazards and non-robust tests. The algebra and implication tables eliminate the necessity to re-examine off-path inputs for a target path to determine the test validity. We provide examples to show that additional values at flip-flop inputs must be justified. This leads to identification of robust untestable faults without search. For the first time we present experimental results on robust and validatable non-robust test generation for ISCAS '89 sequential circuits in the non-scan mode using a variable clock scheme. Our test generator runs 26 times faster than previously published results for sequential circuits.