Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
DAC '77 Proceedings of the 14th Design Automation Conference
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
On the fault coverage of delay fault detecting tests
EURO-DAC '90 Proceedings of the conference on European design automation
DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits
EURO-DAC '92 Proceedings of the conference on European design automation
Design for testability for path delay faults in sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
An efficient path delay fault coverage estimator
DAC '94 Proceedings of the 31st annual Design Automation Conference
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Deriving Logic Systems for Path Delay Test Generation
IEEE Transactions on Computers
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Generating Tests for Delay Faults in Nonscan Circuits
IEEE Design & Test
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Functional test generation for path delay faults
ATS '95 Proceedings of the 4th Asian Test Symposium
Sequential logic path delay test generation by symbolic analysis
ATS '95 Proceedings of the 4th Asian Test Symposium
A trace-based method for delay fault diagnosis in synchronous sequential circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
An efficient method for computing exact path delay fault coverage
EDTC '95 Proceedings of the 1995 European conference on Design and Test
DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Robust testing for stuck-at faults
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A graph approach to DFT hardware placement for robust delay fault BIST
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Statistical path delay fault coverage estimation for synchronous sequential circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Effective Path Selection for Delay Fault Testing of Sequential Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Beyond two
Fault simulation and random test generation for speed-independent circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A delay fault model for at-speed fault simulation and test generation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Exploiting MOEA to automatically geneate test programs for path-delay faults in microprocessors
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
On path delay testing in a standard scan environment
ITC'94 Proceedings of the 1994 international conference on Test
Effective diagnostic pattern generation strategy for transition-delay faults in full-scan SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft-error tolerance and mitigation in asynchronous burst-mode circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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