Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Equivalence of robust delay-fault and single stuck-fault test generation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay fault test generation for scan/hold circuits using Boolean expressions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Boolean algebraic test generation using a distributed system
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A method of delay fault test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
On Multiple Path Propagating Tests for Path Delay Faults
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
On the fault coverage of delay fault detecting tests
EURO-DAC '90 Proceedings of the conference on European design automation
Digital sensitivity: predicting signal interaction using functional analysis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Hierarchical Delay Test Generation
Journal of Electronic Testing: Theory and Applications
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
ATPG tools for delay faults at the functional level
DATE '99 Proceedings of the conference on Design, automation and test in Europe
SAT based ATPG using fast justification and propagation in the implication graph
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Distributed BIST Architecture to Combat Delay Faults
Journal of Electronic Testing: Theory and Applications
ATPG tools for delay faults at the functional level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay fault testing of IP-based designs via symbolic path modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Functional test generation for path delay faults
ATS '95 Proceedings of the 4th Asian Test Symposium
Sequential logic path delay test generation by symbolic analysis
ATS '95 Proceedings of the 4th Asian Test Symposium
ATPG for Path Delay Faults without Path Enumeration
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Delay Fault Testing of IP-Based Designs Via Symbolic Path Modeling
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Low power ATPG for path delay faults
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Static Verification of Test Vectors for IR Drop Failure
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Non-Enumerative Path Delay Fault Diagnosis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Functions for Quality Transition Fault Tests
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Low power test generation for path delay faults using stability functions
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Test set enhancement for quality transition faults using function-based methods
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
SAT-based ATPG using multilevel compatible don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
Journal of Electronic Testing: Theory and Applications
Exploiting MOEA to automatically geneate test programs for path-delay faults in microprocessors
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
Identification of delay measurable PDFs using linear dependency relationships
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Function-based compact test pattern generation for path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 14.99 |
A new test generation technique for path delay faults in circuits employing scan/hold type flip-flops is presented. Reduced ordered binary decision diagrams (ROBDDs) are used to represent Boolean functions realized by all signals in the circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit. For each fault, a pair of constraint functions, corresponding to the two time frames that constitute a transition, is evaluated. If the constraint function in the second time frame is non-null, robust - hazard-free - test generation for the delay fault is attempted. A robust test thus generated belongs either to the class of fully transitional path (FTP) tests or to the class of single input transition (SIT) tests. If a robust test cannot be found, the existence of a non-robust test is checked. Boolean algebraic manipulation of the constraint functions guarantees that if neither robust nor non-robust tests exist, the fault is undetectable. In its present form the method is applicable to all circuits that are amenable to analysis using ROBDDs. An implementation of this technique is used to analyze delay fault testability of ISCAS 驴89 benchmark circuits. These results show that the algebraic technique is one to two orders of magnitude faster than previously reported methods based on branch-and-bound algorithms.