Delay fault test generation for scan/hold circuits using Boolean expressions

  • Authors:
  • D. Bhattacharya;P. Agrawal;V. D. Agrawal

  • Affiliations:
  • Yale University, P.O. Box 2157, Yale Station, New Haven, CT;AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, NJ;-

  • Venue:
  • DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
  • Year:
  • 1992

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Abstract