Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A method of delay fault test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
RESIST: a recursive test pattern generation algorithm for path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
BiTeS: a BDD based test pattern generator for strong robust path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Path delay ATPG for standard scan design
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A satisfiability-based test generator for path delay faults in combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Ordered Binary Decision Diagrams and Minimal Trellises
IEEE Transactions on Computers
ATPG tools for delay faults at the functional level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Path delay fault testing using test points
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Testability forecasting for sequential circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Bit parallel test pattern generation for path delay faults
EDTC '95 Proceedings of the 1995 European conference on Design and Test
An efficient automatic test generation system for path delay faults in combinational circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On path delay testing in a standard scan environment
ITC'94 Proceedings of the 1994 international conference on Test
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