Delay fault test generation for scan/hold circuits using Boolean expressions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An algorithm to reduce test application time in full scan designs
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Sequential circuit test generation on a distributed system
DAC '93 Proceedings of the 30th international Design Automation Conference
A Test-Pattern-Generation Algorithm for Sequential Circuits
IEEE Design & Test
An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
Sequential Test Generation Based on Real-Value Logic
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Small Test Generator for Large Designs
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
| Hi-index | 0.00 |
Of all the developments of testable as well as reliable designs for computing systems, test generations for sequential circuits are usually viewed as one of the hard nuts to be solved in terms of complexity and time-consumption. Although some dozens of algorithms have been proposed to cope with these issues, much still remains to be desired in solving such problems so as to determine: (1) which of the existing test generation algorithms could be the most efficient for some particular circuits; (2) which parameters will have the most or least influences on test generations. For this purpose, a testability forecasting method for sequential circuits using regression models has been presented which a user usually needs for analyzing their own circuits and selecting the most suitable test generation algorithm from all possible algorithms available. Some examples and experimental results are also provided in order to show how helpful and practical the method is.