A Small Test Generator for Large Designs

A formal non-heuristic ATPG approach

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation

Efficient orthonormality testing for synthesis with pass-transistor selectors

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Efficient use of large don't cares in high-level and logic synthesis

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

BooleDozer: logic synthesis for ASICs

IBM Journal of Research and Development

Verification of large synthesized designs

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Minimum area retiming with equivalent initial states

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Optimal FPGA mapping and retiming with efficient initial state computation

DAC '98 Proceedings of the 35th annual Design Automation Conference

Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation

Journal of Electronic Testing: Theory and Applications

Circuit-based Boolean Reasoning

Proceedings of the 38th annual Design Automation Conference

Performance-constrained pipelining of software loops onto reconfigurable hardware

FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays

Flexibillity in logic

Logic Synthesis and Verification

New Techniques for Deterministic Test Pattern Generation

Journal of Electronic Testing: Theory and Applications

ATPG in practical and non-traditional applications

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Testability forecasting for sequential circuits

ATS '95 Proceedings of the 4th Asian Test Symposium

Improving initialization through reversed retiming

EDTC '95 Proceedings of the 1995 European conference on Design and Test

20.2 New Techniques for Deterministic Test Pattern Generation

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Bridge and brick network motifs: Identifying significant building blocks from complex biological systems

Artificial Intelligence in Medicine

Retiming: Theory and practice

Integration, the VLSI Journal