Efficient use of large don't cares in high-level and logic synthesis

Authors:
R. A. Bergamaschi;D. Brand;L. Stok;M. Berkelaar;S. Prakash
Affiliations:
IBM T. J. Watson Research Center, NY;IBM T. J. Watson Research Center, NY;IBM T. J. Watson Research Center, NY;Eindhoven University of Technology, Eindhoven, The Netherlands;Mentor Graphics Corp., Wilsonville, OR
Venue:
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Year:
1995

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Abstract

This paper describes optimization techniques using don't-care conditions that span the domain of high-level and logic synthesis. The following three issues are discussed: 1) how to describe and extract don't-care conditions from high-level descriptions; 2) how to pass don't-care conditions from high-level to logic synthesis; and 3) how to optimize the logic using don't-care conditions. Efficient techniques are given for these three problems which allow the use of large don't-care sets. Results from several examples demonstrate that these techniques are very effective for both area and delay minimization.