ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient use of large don't cares in high-level and logic synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
A two-state methodology for RTL logic simulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Automatic formal verification of DSP software
Proceedings of the 37th Annual Design Automation Conference
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
SAT-Based Complete Don't-Care Computation for Network Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SAT sweeping with local observability don't-cares
Proceedings of the 43rd annual Design Automation Conference
The coming of age of (academic) global routing
Proceedings of the 2008 international symposium on Physical design
Functional Design Errors in Digital Circuits: Diagnosis Correction and Repair
Functional Design Errors in Digital Circuits: Diagnosis Correction and Repair
Ad-Hoc Translations to Close Verilog Semantics Gap
DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Finding reset nondeterminism in RTL designs: scalable X-analysis methodology and case study
Proceedings of the Conference on Design, Automation and Test in Europe
Optimizing blocks in an SoC using symbolic code-statement reachability analysis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Improving gate-level simulation accuracy when unknowns exist
Proceedings of the 49th Annual Design Automation Conference
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Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle such conditions accurately at the behavior and register transfer levels, which is problematic since the trend is to move toward high-level synthesis. In this work we propose innovative methods to handle such conditions accurately at high-level designs. In addition, we propose two novel algorithms based on our new methods to minimize the number of registers that need to be initialized at the architecture level, which can reduce the routing resources used by the reset signals and alleviate the routing problem. Our results show that we can identify 53% of the registers that can be uninitialized in a 5-stage pipelined processor within 5 minutes, demonstrating the effectiveness of our approach.