The coming of age of (academic) global routing

Authors:
Michael D. Moffitt;Jarrod A. Roy;Igor L. Markov
Affiliations:
IBM Austin Research Lab, Austin, TX, USA;University of Michigan, Ann Arbor, MI, USA;University of Michigan, Ann Arbor, MI, USA and Synplicity Inc., Sunnyvale, CA
Venue:
Proceedings of the 2008 international symposium on Physical design
Year:
2008

Citing 37
Cited 11

PathFinder: a negotiation-based performance-driven router for FPGAs

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Improved algorithms for hypergraph bipartitioning

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Estimating routing congestion using probabilistic analysis

Proceedings of the 2001 international symposium on Physical design
Accurate pseudo-constructive wirelength and congestion estimation

Proceedings of the 2003 international workshop on System-level interconnect prediction
Improved global routing through congestion estimation

Proceedings of the 40th annual Design Automation Conference
Global wiring on a wire routing machine

DAC '82 Proceedings of the 19th Design Automation Conference
Probabilistic congestion prediction

Proceedings of the 2004 international symposium on Physical design
Congestion prediction in early stages

Proceedings of the 2005 international workshop on System level interconnect prediction
Is probabilistic congestion estimation worthwhile?

Proceedings of the 2005 international workshop on System level interconnect prediction
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield

ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
FLUTE: fast lookup table based wirelength estimation technique

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A novel framework for multilevel full-chip gridless routing

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Highly scalable algorithms for rectilinear and octilinear Steiner trees

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
mPL6: enhanced multilevel mixed-size placement

Proceedings of the 2006 international symposium on Physical design
Architecture and details of a high quality, large-scale analytical placer

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
BoxRouter: a new global router based on box expansion and progressive ILP

Proceedings of the 43rd annual Design Automation Conference
Novel full-chip gridless routing considering double-via insertion

Proceedings of the 43rd annual Design Automation Conference
Electronic Design Automation for Integrated Circuits Handbook - 2 Volume Set

Electronic Design Automation for Integrated Circuits Handbook - 2 Volume Set
Efficient obstacle-avoiding rectilinear steiner tree construction

Proceedings of the 2007 international symposium on Physical design
FastRoute: a step to integrate global routing into placement

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Optimizing yield in global routing

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Probabilistic Congestion Prediction with Partial Blockages

ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
IPR: an integrated placement and routing algorithm

Proceedings of the 44th annual Design Automation Conference
FastRoute 2.0: A High-quality and Efficient Global Router

ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm

ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
The coming of age of physical synthesis

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Archer: a history-driven global routing algorithm

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
High-performance routing at the nanometer scale

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
MaizeRouter: engineering an effective global router

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A new global router for modern designs

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A global router with a theoretical bound on the optimal solution

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing by new approximation algorithms for multicommodity flow

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pattern routing: use and theory for increasing predictability and avoiding coupling

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Benchmarking for large-scale placement and beyond

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MARS-a multilevel full-chip gridless routing system

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Handling don't-care conditions in high-level synthesis and application for reducing initialized registers

Proceedings of the 46th Annual Design Automation Conference
Global routing revisited

Proceedings of the 2009 International Conference on Computer-Aided Design
What makes a design difficult to route

Proceedings of the 19th international symposium on Physical design
Accurately handle don't-care conditions in high-level designs and application for reducing initialized registers

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Finding reset nondeterminism in RTL designs: scalable X-analysis methodology and case study

Proceedings of the Conference on Design, Automation and Test in Europe
Network-on-Chip interconnect for pairing-based cryptographic IP cores

Journal of Systems Architecture: the EUROMICRO Journal
Wire synthesizable global routing for timing closure

Proceedings of the 16th Asia and South Pacific Design Automation Conference
Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Exploring high throughput computing paradigm for global routing

Proceedings of the International Conference on Computer-Aided Design
FastRoute: an efficient and high-quality global router

VLSI Design
BonnRoute: Algorithms and data structures for fast and good VLSI routing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Quantified Score

Hi-index	0.00

Visualization

Abstract

Wire routing, an important step in modern VLSI design, is increasingly responsible for timing closure and manufacturability. The CAD community has witnessed remarkable improvements in speed and quality of global routing algorithms in response to the inaugural ISPD 2007 Global Routing Contest, where prizes were awarded for best results on a new set of large industry benchmarks. In this paper, we review the state of the art in global routing and identify several critical techniques that distinguish top routing algorithms. We also discuss open challenges and offer predictions regarding the future of routing research.