Introduction to algorithms
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
An Introduction to VLSI Physical Design
An Introduction to VLSI Physical Design
Efficient Steiner tree construction based on spanning graphs
Proceedings of the 2003 international symposium on Physical design
Proceedings of the 2004 international symposium on Physical design
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
Proceedings of the 2005 international symposium on Physical design
A tale of two nets: studies of wirelength progression in physical design
Proceedings of the 2006 international workshop on System-level interconnect prediction
Seeing the forest and the trees: Steiner wirelength optimization in placemen
Proceedings of the 2006 international symposium on Physical design
BoxRouter: a new global router based on box expansion and progressive ILP
Proceedings of the 43rd annual Design Automation Conference
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
Fast and robust quadratic placement combined with an exact linear net model
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fast and accurate routing demand estimation for efficient routability-driven placement
Proceedings of the conference on Design, automation and test in Europe
IPR: an integrated placement and routing algorithm
Proceedings of the 44th annual Design Automation Conference
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Metal-density driven placement for cmp variation and routability
Proceedings of the 2008 international symposium on Physical design
The coming of age of (academic) global routing
Proceedings of the 2008 international symposium on Physical design
MaizeRouter: engineering an effective global router
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
An innovative Steiner tree based approach for polygon partitioning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FastRoute3.0: a fast and high quality global router based on virtual capacity
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Analog placement with common centroid and 1-D symmetry constraints
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
FastRoute 4.0: global router with efficient via minimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 international symposium on Physical design
Multilayer global routing with via and wire capacity considerations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A power-efficient multipin ILP-based routing technique
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Pulsed-latch aware placement for timing-integrity optimization
Proceedings of the 47th Design Automation Conference
Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Efficient congestion mitigation using congestion-aware steiner trees and network coding topologies
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs
Proceedings of the 24th symposium on Integrated circuits and systems design
| Hi-index | 0.00 |
Wirelength estimation is an important tool to guide the design optimization process in early design stages. In this paper, we present a wirelength estimation technique called FLUTE. Our technique is based on pre-computed lookup table to make wirelength estimation very fast and very accurate for low degree nets. We show experimentally that for FLUTE, RMST, and HPWL, the average error in wirelength are 0.72%, 4.23%, and -8.71%, respectively, and the normalized runtime are 1, 1.24, and 0.16, respectively.