RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Speed and area tradeoffs in cluster-based FPGA architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Estimating routing congestion using probabilistic analysis
Proceedings of the 2001 international symposium on Physical design
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Interconnect resource-aware placement for hierarchical FPGAs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An architectural exploration of via patterned gate arrays
Proceedings of the 2003 international symposium on Physical design
Synthesis and placement flow for gain-based programmable regular fabrics
Proceedings of the 2003 international symposium on Physical design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Congestion minimization during placement without estimation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Incremental placement for layout driven optimizations on FPGAs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
Wire length prediction based clustering and its application in placement
Proceedings of the 40th annual Design Automation Conference
Design automation for mask programmable fabrics
Proceedings of the 41st annual Design Automation Conference
Routing architecture exploration for regular fabrics
Proceedings of the 41st annual Design Automation Conference
The Magic of a Via-Configurable Regular Fabric
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Is probabilistic congestion estimation worthwhile?
Proceedings of the 2005 international workshop on System level interconnect prediction
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
Proceedings of the 2005 international symposium on Physical design
Routability-driven placement and white space allocation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
FLUTE: fast lookup table based wirelength estimation technique
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An effective congestion-driven placement framework
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routability-driven white space allocation for fixed-die standard-cell placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The impact of interconnect architecture on via-programmed structured ASICs (VPSAs)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Via configurable three-input lookup-tables for structured ASICs
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Power gating design for standard-cell-like structured ASICs
Proceedings of the Conference on Design, Automation and Test in Europe
Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Routability optimization for crossbar-switch structured ASIC design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design and analysis of via-configurable routing fabrics for structured ASICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A regular fabric design methodology for applications requiring specific layout-level design rules
Microelectronics Journal
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In this paper, we describe a new via-configurable routing architecture which shows a much better throughput and performance than the previous structures. We demonstrate how to construct a single-via-mask fabric to reduce the mask cost further, and we analyze the penalties which it incurs. To solve the routability problem commonly existing in fabric-based designs, an efficient white-space allocation and an incremental cell movement scheme are suggested, which help to provide a fast design convergence and early prediction of circuit's mappability to a given fabric.