On routability prediction for field-programmable gate arrays
DAC '93 Proceedings of the 30th international Design Automation Conference
An architecture-independent approach to FPGA routing based on multi-weighted graphs
EURO-DAC '94 Proceedings of the conference on European design automation
FPGA routing and routability estimation via Boolean satisfiability
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
RPack: routability-driven packing for cluster-based FPGAs
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Graph based analysis of 2-D FPGA routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generating synthetic benchmark circuits for evaluating CAD tools
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Efficient circuit clustering for area and power reduction in FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Whirlpool PLAs: a regular logic structure and their synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Congestion minimization during placement without estimation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Modeling instruction placement on a spatial architecture
Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures
A novel approach to the placement and routing problems for field programmable gate arrays
Applied Soft Computing
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An analytical model relating FPGA architecture parameters to routability
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Towards development of an analytical model relating FPGA architecture parameters to routability
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
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In this paper, we utilize Rent's rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design complexity and architecture resources of hierarchical FPGAs can have a positive impact on the overall device area. We propose a circuit placement algorithm based on Rent's parameter and show that our clustering and placement techniques can improve the overall device routing area by as much as 21% for the same array size, when compared to a state-of-art FPGA placement and routing tool.