Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Efficient and effective placement for very large circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A timing driven N-way chip and multi-chip partitioner
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Performance of a new annealing schedule
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A priori system-level interconnect prediction: Rent's rule and wire length distribution models
Proceedings of the 2001 international workshop on System-level interconnect prediction
On rent's rule for rectangular regions
Proceedings of the 2001 international workshop on System-level interconnect prediction
Congestion estimation during top-down placement
Proceedings of the 2001 international symposium on Physical design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Interconnect resource-aware placement for hierarchical FPGAs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Timing analysis of computer hardware
IBM Journal of Research and Development
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This work explores the effect of adding a new partitioning step into the traditional complex programmable logic device (CPLD) CAD flow. A novel algorithm based on Rent's rule and simulated annealing partitions a design before it enters the place and route stage in CPLD CAD. The resulting partitions are then placed using an enhanced placement tool. Experiments conducted on Altera'a APEX20K chips indicate that a partitioned placement can provide an average performance gain of 7% over flat placements.