Congestion estimation during top-down placement

  • Authors:
  • Xiaojian Yang;Ryan Kastner;Majid Sarrafzadeh

  • Affiliations:
  • Computer Science Department, University of California at Los Angeles, Los Angeles, CA;Computer Science Department, University of California at Los Angeles, Los Angeles, CA;Computer Science Department, University of California at Los Angeles, Los Angeles, CA

  • Venue:
  • Proceedings of the 2001 international symposium on Physical design
  • Year:
  • 2001

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Abstract

Congestion is one of the fundamental issues in VLSI physical design. In this paper, we propose two congestion estimation approaches for early placement stages. First, we theoretically analyze the peak congestion value of the design and experimentally validate the estimation approach. Second, we estimate regional congestion in the early top-down placement. This is done by combining the wirelength distribution model and inter-region wire estimation. Both approaches are based on the well known Rent's rule, which is previously used for wirelength estimation. This is the first attempt to predict congestion using Rent's rule. The estimation results are compared with the layout after placement and global routing. Experiments on large industry circuits show that the early congestion estimation based on Rent's rule is a promising approach.